HyperLUT Update Circuits for Faster Low-Data LUT Reconfiguration
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Solution Overview
Problem
Updating pre-computed results in large lookup tables (LUTs) within processors is time and energy-intensive due to the need to propagate significant amounts of data, which hampers the efficiency of artificial intelligence and SIMD operations.
Innovation Solution
The implementation of an augmented multi-port lookup table (HyperLUT) with transformation units that propagate raw, partial, or compressed data to minimize the amount of data transferred, using multiple read ports and memory sub-structures to reduce memory requirements and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pre-computed results are stored in large LUTs for fast retrieval, then access speed is improved, but updating the results becomes time and energy-intensive due to large data propagation requirements
Solution Approach 1:
The LUT is divided into multiple sub-LUTs (e.g., first and second sub-LUTs) that can be updated independently or in parallel. This segmentation allows the update process to be distributed across multiple smaller units, reducing the overall time and energy required to update the entire LUT while maintaining fast access capabilities through the combined structure.
Solution Approach 2:
The patent introduces a third dimension to the traditional LUT structure by adding a sub-LUT dimension. Instead of a single flat LUT, the structure becomes hierarchical with multiple sub-LUTs that can be selectively accessed and updated. This dimensional change enables parallel update operations and reduces the propagation distance for configuration data, thereby decreasing update time while preserving fast retrieval speed.
2Speed
If pre-computed results are stored in large LUTs for fast retrieval, then access speed is improved, but energy consumption increases due to the significant data propagation required
Solution Approach 1:
By segmenting the LUT into multiple sub-LUTs, the data propagation required for updates is divided into smaller, parallel tasks. Each sub-LUT receives and processes a portion of the configuration data, reducing the energy consumption per unit while maintaining the overall fast access performance through the combined structure.
Solution Approach 2:
The hierarchical sub-LUT structure adds a dimensional layer that enables more efficient data distribution. Configuration data can be propagated to multiple sub-LUTs simultaneously through dedicated pathways, reducing the total energy consumption compared to updating a single large LUT sequentially, while preserving fast access speed through the multi-sub-LUT architecture.
3Adaptability or versatility
If multiple single-port LUTs are used to achieve the same number of read ports as an augmented LUT, then read port capacity is matched, but more data is required and propagation becomes more time and energy-intensive
Solution Approach 1:
Multiple sub-LUTs are merged into a single augmented LUT structure that shares common configuration data. Instead of each single-port LUT requiring its own complete set of pre-computed results, the sub-LUTs share a common data space, reducing the total data volume required while maintaining the same read port capacity through coordinated access to the shared structure.
Solution Approach 2:
The augmented LUT structure provides universal access capabilities where a single configuration data set serves multiple read ports simultaneously. The sub-LUTs are designed to share common configuration information, allowing the same data to be utilized across multiple access points, thereby reducing the total quantity of data needed compared to separate single-port LUTs while maintaining equivalent read port capacity.
4Adaptability or versatility
If multiple single-port LUTs are used to achieve the same number of read ports as an augmented LUT, then read port capacity is matched, but propagation time and energy increase
Solution Approach 1:
The sub-LUTs are merged into a unified augmented LUT structure with shared configuration data pathways. This merging enables simultaneous propagation of configuration data to multiple sub-LUTs through common buses and interconnects, reducing the total propagation time compared to updating separate single-port LUTs independently, while maintaining the same read port capacity through the combined structure.
Solution Approach 2:
The hierarchical structure introduces a sub-LUT dimension that enables parallel data propagation pathways. Configuration data can be distributed to multiple sub-LUTs simultaneously through the added dimensional layer, reducing the propagation time required to update the entire structure while maintaining equivalent read port capacity compared to a flat arrangement of single-port LUTs.
Data Source
AI summary
The present disclosure provides circuits and methods that can be used to update configurations. An example circuit can include a plurality hLUTs and a plurality of registers configured to propagate a set of data or a portion thereof to the plurality of hLUTs. An hLUT of the plurality of hLUTs can have a transformation unit comprising transformation circuitry configured to (i) receive the set of data or the portion thereof from a register of the plurality of registers and (ii) transform the set of data or the portion thereof into configurations for the hLUT.