Hypervault Memory Module DRAM Flash Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory modules, particularly those using DRAM, face challenges with volatility, high cost, and limited capacity compared to Flash memory, necessitating a solution that integrates volatile and non-volatile subsystems efficiently to enhance performance and capacity while minimizing data loss and access conflicts.
Innovation Solution
The integration of a Hypervault™ memory module with both DRAM and Flash memory, utilizing a module control subsystem that includes a buffer memory and data routing circuit to manage data transfers between DRAM and Flash, ensuring efficient data buffering and error correction, and utilizing control logic to handle page faults and data access conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used as system memory, then access speed is improved, but data volatility and cost increase
Solution Approach 1:
The memory system is segmented into two distinct subsystems: a volatile DRAM subsystem for high-speed access and a non-volatile Flash subsystem for persistent storage. The controller intelligently partitions memory operations between these subsystems, allowing fast access to frequently used data in DRAM while maintaining reliability through Flash storage for critical data.
Solution Approach 2:
A buffer memory subsystem is introduced as an intermediary between the DRAM and Flash memory subsystems. This buffer acts as a mediator that temporarily holds data during transfers between the volatile and non-volatile memory, smoothing out access patterns and reducing the impact of DRAM volatility while maintaining system performance.
2Quantity of substance
If DRAM density is increased, then memory capacity is improved, but cost increases significantly
Solution Approach 1:
The system merges DRAM and Flash memory technologies into a unified memory module. By combining the high-speed access characteristics of DRAM with the high-density, low-cost characteristics of Flash memory, the system achieves large memory capacity at reduced cost compared to using high-density DRAM alone.
Solution Approach 2:
The system changes the storage density parameter by utilizing Flash memory technology, which offers significantly higher density than DRAM. This parameter change allows the system to achieve terabyte-scale capacity while maintaining cost-effectiveness, as Flash memory can be manufactured at lower costs per gigabyte compared to high-density DRAM.
3Ease of manufacture
If Flash memory is used instead of DRAM, then cost and capacity are improved, but access speed decreases
Solution Approach 1:
The memory system applies local quality by optimizing different regions for different purposes: the DRAM subsystem handles frequently accessed data requiring high speed, while the Flash subsystem stores less frequently accessed data where cost and capacity are more important. This spatial and functional differentiation allows the system to achieve both speed and cost efficiency simultaneously.
4Quantity of substance
If a hybrid memory system is implemented, then capacity and cost are improved, but device complexity increases
Solution Approach 1:
The controller is designed with multi-functionality to manage both DRAM and Flash memory subsystems, as well as the buffer memory. This universal controller handles memory management, data transfer coordination, error correction, and address translation across all three memory types, simplifying the overall system architecture despite the complexity of the hybrid memory configuration.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in a computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the memory channel. The module controller reads first data from the non-volatile memory subsystem and reads second data from the volatile memory subsystem in response to a NV access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory channel.