Hypervisor Idle State Selection Using Residency Feedback Loops

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Solution Overview

Problem

Hypervisors in virtualized environments struggle to accurately select processor idle states due to lack of visibility into guest virtual machine workloads, leading to inefficient energy consumption and performance issues.

Innovation Solution

A hypervisor-based method using a combination of simple moving average (SMA) and exponential moving average (EMA) calculations in a feedback loop to project processor idle residency, dynamically adjusting idle state selection to improve accuracy and balance energy savings with performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a deeper idle state is selected to reduce power consumption, then energy efficiency is improved, but exit latency increases causing performance degradation

Engineering Contradiction:

Improveprocessor power consumptionVSAvoidexit latency

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent implements dynamic idle state selection by the hypervisor based on projected idle residency. The system continuously monitors workload patterns and adjusts the depth of idle states (C-states) in real-time, transitioning from static to dynamic control. This allows the processor to adaptively choose between lighter (lower exit latency) and deeper (lower power consumption) idle states according to actual workload conditions, resolving the contradiction between energy efficiency and performance.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the hypervisor projects future idle residency based on historical workload data and uses this projection to select appropriate idle states. The system continuously gathers performance data and adjusts idle state selection accordingly, creating a closed-loop control system that balances power consumption and exit latency based on actual system conditions and workload patterns.

Inventive Principle:

Principle #23Feedback

2Speed

If the operating system directly controls idle state selection, then response time is reduced, but visibility into guest VM workloads is lost in virtualized environments

Engineering Contradiction:

Improveidle state selection response timeVSAvoidworkload visibility

Core Design Contradiction:

SpeedVSLoss of information

Solution Approach 1:

The patent introduces the hypervisor as an intermediary layer between the guest operating systems and the physical processor. The hypervisor collects workload information from multiple guest VMs, projects future idle residency, and makes informed idle state selection decisions. This intermediary approach allows the system to maintain visibility into guest VM workloads while still enabling fast idle state transitions, as the hypervisor has direct access to processor controls and comprehensive workload visibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the idle state control function from the guest operating systems and centralizes it in the hypervisor layer. This segmentation allows each guest OS to focus on its own workload management while the hypervisor handles the complex task of idle state selection based on aggregate workload information. The separation of concerns enables the hypervisor to make globally optimal idle state decisions without interfering with guest OS performance.

Inventive Principle:

Principle #1Segmentation

3Loss of energy

If deeper idle states are used to maximize energy savings, then power consumption is reduced, but data throughput decreases due to frequent wake-ups

Engineering Contradiction:

Improveprocessor energy consumptionVSAvoiddata throughput

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The patent performs preliminary action by projecting future idle residency before selecting an idle state. The hypervisor analyzes historical workload patterns and predicts whether the processor will remain idle long enough to justify entering a deeper idle state. This advance planning allows the system to pre-select the optimal idle state depth, avoiding both premature wake-ups (which reduce throughput) and unnecessarily deep idle states (which waste energy), thereby maximizing both energy efficiency and data throughput.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP4682675A1Processor idle state selection in a virtualized environment

Publication Date: 2026.01.21 MICROSOFT TECHNOLOGY LICENSING LLC

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AI summary

A method implemented in a computer system with a processor system, including a logical processor, includes configuring an idle state calculation loop with a first idle residency calculation type, generating a projected processor idle residency, determining a target processor idle state based on the projected residency, instructing the logical processor to enter an idle period using the target state, identifying the actual processor idle residency post-idle period, and comparing it to the projected residency. Based on this comparison, the method configures the idle state calculation loop with a second idle residency calculation type. This method optimizes processor idle states by dynamically adjusting the calculation type to improve power efficiency and performance in the computer system.