Hypervisor Interrupt Routing via MDA Mapping

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Solution Overview

Problem

In virtualized computer systems, the current methods for interrupt routing result in increased latency due to the need to cycle through data structures storing the contents of APIC registers for active virtual processors, which is inefficient and exceeds acceptable processing times.

Innovation Solution

The implementation of a hypervisor-supported data structure that maps message destination addresses (MDA) to virtual processors for both physical and logical interrupt destination modes, allowing for direct identification and routing of interrupts without the need to cycle through APIC register contents, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system cycles through data structures storing APIC register contents to identify virtual processors for interrupt routing, then the system can maintain compatibility with existing interrupt handling mechanisms, but the interrupt processing latency increases beyond acceptable levels

Engineering Contradiction:
Improveinterrupt routing compatibilityVSAvoidinterrupt processing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent pre-computes and stores the mapping between message destination addresses (MDA) and virtual processor identifiers in a dedicated data structure before interrupt handling is needed. This preliminary action eliminates the need to cycle through APIC register contents at interrupt handling time, thus reducing latency while maintaining compatibility with existing interrupt mechanisms that use MDA for virtual processor identification.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the system uses a straightforward data structure mapping approach to reduce interrupt latency, then interrupt processing speed improves, but the device complexity increases due to additional data structures

Engineering Contradiction:
Improveinterrupt processing speedVSAvoiddata structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a simplified copy or projection of the APIC register mapping relationship in the form of an MDA-to-virtual-processor mapping data structure. This copy contains only the essential routing information needed for interrupt handling, eliminating the need to navigate complex nested data structures while preserving the essential routing functionality, thus improving speed without proportionally increasing complexity.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9235538B2Injecting interrupts in virtualized computer systems
Publication Date: 2016.01.12 RED HAT ISRAEL
  • US9235538B2 patent drawing
  • US9235538B2 patent drawing
  • US9235538B2 patent drawing

AI summary

Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address.