Hypervisor IOMMU Translation Bypass for VM Migration

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Solution Overview

Problem

Existing virtualization systems incur significant overhead due to hypervisor address translation, particularly in network function virtualization applications with high access request rates, which can lead to performance degradation and reduced efficiency.

Innovation Solution

The hypervisor configures a host input-output memory management unit to bypass address translation by reserving a range of guest physical addresses, allowing the host IOMMU to handle device access requests directly, thereby reducing the need for hypervisor-mediated translations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the hypervisor performs address translation for device access requests, then the guest virtual machine can access memory through virtual addresses, but the processing overhead increases and performance degrades

Engineering Contradiction:

Improvememory access simplicityVSAvoidrequest processing throughput

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent extracts the address translation function from the hypervisor and relocates it to the host IOMMU. The hypervisor configures the IOMMU with address translation tables, but the actual translation of device access requests is performed by the IOMMU hardware, not the hypervisor software path. This separation removes the translation overhead from the critical request processing path while maintaining the necessary address translation capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The host IOMMU acts as an intermediary between devices and guest virtual machine memory. Instead of the hypervisor directly translating every address translation request, the IOMMU hardware mediates the translation process by intercepting device access requests, translating addresses using pre-configured tables, and completing the access without hypervisor involvement. This intermediary hardware layer eliminates the software overhead while preserving address translation functionality.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the hypervisor handles all device access requests, then address translation can be performed, but the hypervisor processing resources are consumed and fewer requests can be handled

Engineering Contradiction:

Improveaddress translation accuracyVSAvoidnumber of requests handled

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the address translation operation from the hypervisor's processing workload and assigns it to the host IOMMU hardware. The hypervisor retains control by configuring the translation tables, ensuring translation accuracy and security, but the actual translation execution is removed from the hypervisor's request handling path, allowing the hypervisor to focus on higher-level management tasks and handle more requests overall.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the software-based address translation mechanism (hypervisor processing) with a hardware-based mechanism (host IOMMU). This substitution transitions address translation from a software operation that consumes CPU cycles and hypervisor resources to a hardware operation that executes in parallel with minimal impact on the hypervisor, thereby increasing the number of requests the system can handle simultaneously while maintaining translation accuracy through proper configuration.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If address translation is performed for every device access request, then memory protection is maintained, but the processing time increases and efficiency decreases

Engineering Contradiction:

Improvememory protectionVSAvoidaddress translation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by having the hypervisor pre-configure the host IOMMU with address translation tables that map device access requests to appropriate guest virtual machine memory regions. These translation tables are set up in advance, allowing the IOMMU hardware to perform rapid lookups and translations without requiring hypervisor intervention for each individual access request. Memory protection is maintained through the pre-configured translation rules, while translation time is reduced by eliminating per-request software processing.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the software-based address translation process with hardware-based translation in the host IOMMU. This substitution executes address translations in parallel at hardware speed rather than sequential software processing, dramatically reducing the time required for each translation operation. Memory protection is preserved through the hardware enforcement of translation rules configured by the hypervisor, while the time loss per request is minimized through efficient hardware implementation.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10140214B2Hypervisor translation bypass by host IOMMU with virtual machine migration support

Publication Date: 2018.11.27 RED HAT ISRAEL

AI summary

A system and method of translation bypass includes a hypervisor configuring a host input-output memory management unit to translate a guest memory of a guest virtual machine. The hypervisor reserves a first portion of the guest memory. The hypervisor receives, from the guest virtual machine, a guest physical address. The hypervisor stores the guest physical address in the first portion of the guest memory. The hypervisor configures a device to access the first portion of the guest memory to locate a command.