Hypervisor Instruction Replacement for Heterogeneous ISA VM Execution
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Solution Overview
Problem
Existing virtualization technologies face challenges in efficiently executing virtual machines with different instruction set architectures (ISAs) due to unsupported or privileged instructions, leading to performance bottlenecks and simulation overhead.
Innovation Solution
A hypervisor system that detects and replaces unsupported or privileged instructions with compatible instructions, while managing memory permissions to enable direct execution on the host processor, thereby emulating the target ISA without full simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If full simulation of target ISA is used, then compatibility is improved, but performance deteriorates due to simulation overhead
Solution Approach 1:
The patent segments instruction execution into two categories: supported instructions that execute natively on the host processor and unsupported instructions that require emulation. This segmentation allows the system to maintain high performance for native instructions while providing compatibility for emulated instructions, resolving the contradiction between performance and adaptability.
Solution Approach 2:
The hypervisor acts as an intermediary layer between the virtual machine and the host processor. It intercepts unsupported instructions and translates/emulates them using host processor instructions, enabling ISA compatibility without requiring full simulation of the target architecture, thus maintaining performance.
2Adaptability or versatility
If unsupported instructions are emulated, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the necessary emulation functionality for unsupported instructions from a full simulator. Instead of implementing complete target ISA simulation, the system extracts and implements only the emulation needed for heterogenous instruction support, reducing complexity while maintaining adaptability.
Solution Approach 2:
The system implements partial emulation by handling only the unsupported instructions that arise in heterogenous ISA scenarios, rather than implementing complete emulation of all target ISA features. This partial action approach reduces complexity while providing sufficient adaptability for the intended use case.
3Productivity
If instruction replacement is performed, then execution performance is improved, but reliability may deteriorate due to permission management
Solution Approach 1:
The patent applies preliminary action by setting execute permissions on memory pages before instruction replacement occurs. The hypervisor ensures that only pages with appropriate execute permissions are modified, preventing unauthorized or incorrect instruction replacements. This preliminary permission check maintains reliability while enabling performance improvement through replacement.
Solution Approach 2:
The system uses feedback mechanisms through exception handling to verify permission validity during instruction replacement. When permission faults occur, the hypervisor receives feedback and adjusts the replacement process accordingly, ensuring that only valid and safe instruction replacements are performed, thus maintaining reliability.
Data Source
AI summary
A method includes: executing, on a host computer including a host processor and host memory, a hypervisor managing a virtual machine including a virtual processor and virtual machine memory, the virtual machine executing a guest program stored in the virtual machine memory, the guest program including machine instructions; disabling, by the hypervisor, execute permissions on a first page of the virtual machine memory; and handling, by the hypervisor, a first abort triggered when the virtual processor executes an instruction in the first page of the virtual machine memory having an execute permission disabled including: replacing, by the hypervisor, one or more instructions in the first page of the virtual machine memory; disabling read and write permissions and enabling an execute permission in a first entry of a page table corresponding to the first page of the virtual machine memory; and resuming execution of the guest program on the virtual processor.