Hypervisor Page Table Mappings for PCI Device Assignment
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Solution Overview
Problem
Current virtualization systems face challenges in efficiently managing peripheral component interconnect (PCI) device assignments and memory access for virtual machines, leading to suboptimal resource utilization and increased overhead due to the need for frequent hypervisor exits.
Innovation Solution
The system employs a hypervisor that generates page tables with mappings between guest and host operating system addresses, modifying access statuses to render host device memory accessible to virtual machine functions, allowing direct access without hypervisor intervention, thereby reducing overhead and enhancing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the hypervisor manages PCI device assignments and memory access for virtual machines, then resource utilization and security are improved, but system overhead increases and performance decreases due to frequent hypervisor exits
Solution Approach 1:
The hypervisor performs preliminary actions by creating page tables and establishing address mappings between guest and host address spaces during virtual machine initialization. This preliminary configuration enables direct memory access for PCI device operations, eliminating the need for frequent hypervisor exits during runtime device assignments and reducing time loss from context switches.
Solution Approach 2:
The patent introduces page tables as an intermediary mechanism between the virtual machine's guest address space and the host's physical address space. These page tables enable indirect address translation, allowing the hypervisor to manage PCI device assignments and memory access without requiring direct intervention for each operation, thus reducing overhead while maintaining security and resource control.
2Reliability
If the hypervisor intervenes in every PCI device assignment and memory access, then security and resource management are improved, but system complexity and overhead increase
Solution Approach 1:
The patent segments the address space management into two distinct layers: guest address space (visible to virtual machines) and host address space (physical memory). Page tables are used to segment and map these address spaces, allowing the hypervisor to manage PCI device assignments and memory access at the page level rather than requiring intervention for every individual access, thus reducing system complexity while maintaining reliable resource management.
Solution Approach 2:
The virtual machines are enabled to self-service PCI device assignments and memory access operations through directly mapped address spaces. The hypervisor configures the initial page tables and access permissions, but subsequent device assignments and memory accesses are handled automatically by the address translation mechanism without requiring continuous hypervisor intervention, reducing complexity while maintaining security.
3Productivity
If direct memory access is enabled for virtual machines, then performance is improved by reducing hypervisor exits, but security control and resource isolation may be compromised
Solution Approach 1:
The patent applies local quality by configuring specific page table entries with different access permissions for different memory regions. Certain pages are marked as readable/writable/executable for virtual machines, while other regions maintain restricted access. This granular, location-specific access control enables direct memory access for performance-critical operations while maintaining security control and resource isolation for sensitive areas.
Solution Approach 2:
The hypervisor dynamically changes parameters in the page tables, such as presence bits, read/write permissions, and executable flags, based on the specific PCI device assignment and memory access requirements. This parameter-based control mechanism allows flexible security policies to be enforced while enabling direct access performance, as the same page table structure can adapt permissions without requiring architectural changes or continuous hypervisor intervention.
Data Source
AI summary
A value stored in a guest device register is received from a virtual machine. A hypervisor generates a page table including a first mapping between the value stored in the guest device register and a first address of the host operating system and a second mapping between a second address of the guest operating system and a third address of a virtual machine function on the host operating system. The hypervisor modifies a first access status of the first mapping to include rendering memory of the host device referenced by the value stored in the guest device register accessible to the virtual machine function, and a second access status of the second mapping to include rendering the virtual machine function accessible to the virtual machine. The hypervisor initializes code on the virtual machine function to access the memory of the host device.