Hypervisor Power Management for Virtual Machines

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Solution Overview

Problem

Existing power management techniques for virtualized computer systems lack visibility into guest scheduling decisions, leading to inefficiencies such as increased event handling latency and incorrect CPU power state management, which can result in additional overhead and performance issues.

Innovation Solution

A hypervisor performs power management for virtual machines by assigning target latency times and enumerating power states, mapping processor power states to host power states, and exposing these states to guest operating systems to optimize CPU usage and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the hypervisor places the processor in a lower-power idle state to save energy, then power consumption is reduced, but the latency to handle events increases

Engineering Contradiction:
Improvepower consumptionVSAvoidevent handling latency
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The system dynamically adjusts the processor idle state based on the target latency requirement of the virtual machine. The hypervisor selects from multiple idle states (C0, C1, C2, C3) depending on the latency tolerance, allowing the processor to operate in the most energy-efficient state that still meets the performance requirement

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the parameter of processor idle state selection by introducing target latency as a decision criterion. The hypervisor modifies the C-state selection based on the latency parameter, mapping different latency requirements to different processor power states to optimize the energy-latency tradeoff

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the hypervisor monitors guest scheduling decisions to optimize power management, then power management efficiency is improved, but system complexity increases

Engineering Contradiction:
Improvepower management efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention introduces an intermediary mechanism (hypercalls and data structures) that allows the guest operating system to communicate scheduling decisions to the hypervisor. This intermediary layer enables the hypervisor to obtain visibility into guest scheduling without requiring direct integration or complex monitoring of guest internals

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback by having the guest operating system provide scheduling decision information to the hypervisor through hypercalls. The hypervisor uses this feedback to adjust processor idle state selection, creating a closed-loop control system that optimizes power management based on actual workload conditions

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If the hypervisor uses virtual memory techniques to accommodate more virtual machines, then the number of virtual machines increases, but memory management complexity increases

Engineering Contradiction:
Improvenumber of virtual machinesVSAvoidmemory management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The hypervisor creates virtual copies of physical memory addresses for each virtual machine, allowing multiple VMs to operate with their own virtual address spaces. This copying mechanism enables more VMs to run than physical memory would normally allow, as memory pages are shared and managed through virtual memory translation

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The invention segments the physical memory into pages that can be dynamically allocated and shared among multiple virtual machines. By dividing memory into manageable pages and using virtual memory techniques, the system can accommodate more VMs than physical memory would normally support

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20230131953A1Power management for virtualized computer systems
Publication Date: 2023.04.27 RED HAT INC
  • US20230131953A1 patent drawing
  • US20230131953A1 patent drawing
  • US20230131953A1 patent drawing

AI summary

Aspects of the disclosure provide for mechanisms for memory protection of virtual machines in a computer system. A method of the disclosure includes: determining a plurality of host latency times for a plurality of processor power states of a processor of a host computer system; comparing, by a hypervisor executed on the host computer system, each of the host latency times to a target latency time associated with a virtual machine running on the host computer system; mapping the plurality of processor power states to a plurality of host power states in view of the comparison; and providing the host power states to the virtual machine.