Safety-Certified Hypervisor RTOS Integration for Low-Latency Assurance

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Solution Overview

Problem

Existing functional safety systems require external hardware components and signal paths for error detection and assurance, increasing complexity and latency.

Innovation Solution

Implementing a safety-certified real-time operating system (RTOS) as a guest machine within a hypervisor on an integrated circuit (IC) device, enabling safe operations and assurance checks within the IC without external data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external hardware components and signal paths are used for error detection, then safety assurance is improved, but system complexity increases

Engineering Contradiction:
Improvesafety assuranceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the safety-critical RTOS and hypervisor into a single integrated IC device, eliminating the need for external hardware components. The RTOS executes safety-critical operations while the hypervisor manages virtualization, both within the same device boundary, thus reducing system complexity while maintaining safety assurance through integrated error detection and monitoring capabilities.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The IC device performs multiple functions including safety-critical operations, error detection, and monitoring all within a single device. The integrated architecture allows the same hardware resources to serve both safety-critical and non-safety-critical functions, reducing the need for dedicated external components while maintaining comprehensive safety assurance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If external hardware components and signal paths are used for error detection, then safety assurance is improved, but latency increases

Engineering Contradiction:
Improvesafety assuranceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By integrating the RTOS and hypervisor within the same IC device, the patent eliminates external signal transmission delays. Error detection and safety monitoring occur internally without the latency introduced by external communication, thus reducing overall system latency while maintaining comprehensive safety assurance.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If safety certified components are used throughout the system, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesafety certificationVSAvoidcertification complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the system into distinct virtual machines with clear safety boundaries. The hypervisor isolates safety-critical RTOS operations from non-safety-critical operations, allowing selective safety certification only for the necessary components while simplifying the overall certification process through clear separation of safety and non-safety functions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260044359A1Functional safety system using safety certified real-time operating system and hypervisor
Publication Date: 2026.02.12 ADVANCED MICRO DEVICES INC
  • US20260044359A1 patent drawing
  • US20260044359A1 patent drawing
  • US20260044359A1 patent drawing

AI summary

An integrated circuit device includes a hardware processor. The integrated circuit device is safety certified. The hardware processor is capable of executing a hypervisor and a real-time operating system (RTOS). The hypervisor is a level 1 hypervisor and is safety certified. The RTOS is safety certified and operates as a first guest machine of the hypervisor. The RTOS is capable of performing a safe operation for a functional safety feature.