Hypervisor vCPU Pinning for Latency-Sensitive Workloads

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing software-defined networking architecture is inefficient in utilizing physical CPUs, as all virtual CPUs (vCPUs) within a virtual machine (VM) are assigned to dedicated physical CPUs (pCPUs) regardless of workload criticality, leading to suboptimal resource allocation and reduced performance.

Innovation Solution

A scheduler in the hypervisor selectively tags vCPUs based on application requirements, ensuring that latency-sensitive vCPUs are pinned to specific pCPUs while non-latency-sensitive vCPUs can be reassigned, optimizing CPU usage by dynamically allocating resources based on workload sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all vCPUs are assigned to dedicated pCPUs, then latency-sensitive workloads maintain high performance, but physical CPU utilization efficiency deteriorates

Engineering Contradiction:
Improvelatency performanceVSAvoidpCPU utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments vCPUs into different categories based on workload characteristics (latency-sensitive vs. non-latency-sensitive). This segmentation allows differential scheduling policies to be applied: latency-sensitive vCPUs are pinned to dedicated pCPUs to ensure low latency, while non-latency-sensitive vCPUs can be dynamically reassigned to improve overall CPU utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating different vCPUs differently based on their specific workload requirements. Instead of a uniform scheduling policy for all vCPUs, the system applies pinned assignment locally to latency-sensitive vCPUs and flexible reassignment locally to non-latency-sensitive vCPUs, optimizing both performance and resource utilization.

Inventive Principle:
Principle #3Local quality

2Productivity

If vCPUs are reassigned to different pCPUs, then physical CPU utilization improves, but latency performance of critical workloads deteriorates

Engineering Contradiction:
ImprovepCPU utilizationVSAvoidlatency performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces dynamics by making the vCPU-to-pCPU assignment policy adaptive rather than static. The scheduling system dynamically determines whether to pin or reassign each vCPU based on real-time workload characteristics, allowing the system to flexibly respond to changing performance requirements while optimizing resource utilization.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the assignment parameter (pinned vs. flexible) based on workload characteristics. By monitoring workload latency sensitivity and adjusting the assignment parameter accordingly, the system optimizes both latency performance and CPU utilization without compromising critical workload performance.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If more VMs are deployed on host computers, then resource consolidation improves, but maintaining high performance for all VMs becomes difficult

Engineering Contradiction:
ImproveVM densityVSAvoidVM performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent enables pCPUs to serve multiple functions by allowing non-latency-sensitive vCPUs from different VMs to share the same pCPU through dynamic reassignment. This multi-functionality increases VM density on host computers while maintaining performance for latency-sensitive workloads through selective pinning.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11429424B2Fine-grained application-aware latency optimization for virtual machines at runtime
Publication Date: 2022.08.30 VMWARE INC
  • US11429424B2 patent drawing
  • US11429424B2 patent drawing
  • US11429424B2 patent drawing

AI summary

A method of selectively assigning virtual CPUs (vCPUs) of a virtual machine (VM) to physical CPUs (pCPUs), where execution of the VM is supported by a hypervisor running on a hardware platform including the pCPUs, includes determining that a first vCPU of the vCPUs is scheduled to execute a latency-sensitive workload of the VM and a second vCPU of the vCPUs is scheduled to execute a non-latency-sensitive workload of the VM and assigning the first vCPU to a first pCPU of the pCPUs and the second vCPU to a second pCPU of the pCPUs. A kernel component of the hypervisor pins the assignment of the first vCPU to the first pCPU and does not pin the assignment of the second vCPU to the second pCPU. The method further comprises selectively tagging or not tagging by a user or an automated tool, a plurality of workloads of the VM as latency-sensitive.