Hypervisor Virtual Processor Priority Interleaving

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Solution Overview

Problem

Current hypervisor scheduling methods do not effectively manage thread priorities within virtual processors, leading to low priority threads being executed on high priority virtual processors instead of high priority threads, resulting in inefficiencies and potential delays in handling interrupts.

Innovation Solution

The hypervisor assigns base priorities to virtual processors and dynamically adjusts these priorities based on thread requirements, temporarily lowering the priority of a virtual processor when an interrupt occurs, allowing higher priority threads to execute and handle interrupts with reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the hypervisor schedules virtual processors based on base priority only, then the scheduling is simple and deterministic, but high priority threads on lower priority virtual processors are not executed promptly

Engineering Contradiction:
Improvethread execution priorityVSAvoidscheduling mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the virtual processor priority adjustable and time-dependent. The hypervisor dynamically modifies the current priority of a virtual processor based on whether it is running a high-priority or low-priority thread, allowing the scheduling behavior to adapt to the actual thread execution needs rather than remaining static at the base priority level

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces an intermediary mechanism (the current priority field) between the base priority and the actual scheduling decision. This intermediary allows the hypervisor to temporarily adjust the effective priority of a virtual processor without changing its base priority, enabling fine-grained control over thread execution while maintaining the virtual processor's identity and long-term scheduling characteristics

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the hypervisor allows low priority threads to execute on high priority virtual processors, then resource utilization is improved, but interrupt handling latency increases

Engineering Contradiction:
Improveresource utilizationVSAvoidinterrupt handling latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by proactively lowering the current priority of a virtual processor before executing a low-priority thread. This prevents high-priority threads from being blocked by low-priority threads on the same virtual processor, ensuring that when a high-priority thread needs to run (or an interrupt occurs), the virtual processor is already in the correct priority state to be scheduled immediately

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by differentiating between different threads within the same virtual processor. Instead of treating the virtual processor as a monolithic entity with a single priority, the system assigns different current priorities based on which thread is currently executing, allowing high-priority threads to get high-priority scheduling while low-priority threads get lower-priority scheduling, all within the same virtual processor context

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9075789B2Methods and apparatus for interleaving priorities of a plurality of virtual processors
Publication Date: 2015.07.07 GENERAL DYNAMICS MISSION SYSTEMS INC
  • US9075789B2 patent drawing
  • US9075789B2 patent drawing
  • US9075789B2 patent drawing

AI summary

Methods and apparatus for interleaving priorities of a plurality of virtual processors are disclosed. A hypervisor assigns a base priority to each virtual processor and schedules one or more virtual processors to execute on one or more physical processors based on the current priority associated with each virtual processor. When the hypervisor receives an indication from one of the virtual processors that its current priority may be temporarily reduced, the hypervisor lowers the current priority of that virtual processor. The hypervisor then schedules another virtual processor to execute on a physical processor instead of the virtual processor with the temporarily reduced priority. When the hypervisor receives an interrupt for the virtual processor with the lowered priority, the hypervisor raises the priority of that virtual processor and schedules the virtual processor with the restored priority to execute on a physical processor so that processor can handle the interrupt.