HyRoC On-Chip Interconnect Minimizes Blocking
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Solution Overview
Problem
Current Network-on-Chip (NoC) architectures, such as the 2D Torus and ClearConnect, face challenges in minimizing internal blocking and routing latency, especially in on-chip implementations, due to their complex scheduling schemes and lack of support for multiple channels and dimensions.
Innovation Solution
The Hyper-Ring-on-Chip (HyRoC) architecture employs a rotation principle with multiple token access, parallel ring channels, and a 2D extension of bidirectional rings, using add-drop multiplexing at each hop to minimize internal blocking and reduce transfer latency, and incorporates a reservation mechanism for different traffic types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a 2D Torus architecture is used with switches connected to form a ring topology, then connectivity and routing flexibility are improved, but internal blocking occurs when traffic for a given source-destination path blocks traffic for an independent source-destination path
Solution Approach 1:
The patent divides the ring topology into multiple independent unidirectional rings (e.g., inner ring and outer ring) that operate separately. Each ring can transport traffic for different source-destination paths without blocking each other, as they are segmented into distinct physical and logical channels. This segmentation eliminates internal blocking while preserving routing flexibility.
Solution Approach 2:
The patent introduces a multi-dimensional ring structure by combining unidirectional rings with bidirectional communication capabilities. Traffic can be routed through different dimensional paths (inner/outer rings, clockwise/counter-clockwise directions), providing additional routing dimensions that avoid blocking issues in a single-plane topology.
2Productivity
If a complex scheduler is used to maximize resource utilization in rotator-switch architecture, then resource utilization is improved, but routing latency increases
Solution Approach 1:
The patent extracts the complex scheduling logic from the data path and implements it at the network interface level rather than at each switch. This allows simple, latency-free switching at the ring level while maintaining high resource utilization through intelligent scheduling at the interface, separating the functions of scheduling and data transmission.
Solution Approach 2:
Instead of using a complex scheduler at each switch to maximize resource utilization (which increases latency), the patent inverts the approach by using simple, deterministic routing at the ring level and implementing complex scheduling only at the network interface. This reverses the traditional approach and reduces latency while maintaining productivity.
3Reliability
If a single ring with multiple parallel channels is used, then internal blocking is minimized, but routing latency increases due to complex scheduling
Solution Approach 1:
The patent segments the ring into multiple unidirectional rings (inner and outer) that operate independently. Each ring can be served by simple scheduling mechanisms since they are separated into distinct physical channels, eliminating the need for complex scheduling while minimizing internal blocking through the segmented structure.
4Device complexity
If basic ring architecture is used, then implementation simplicity is maintained, but scalability and transfer latency are limited
Solution Approach 1:
The patent extends the basic ring architecture to a multi-dimensional structure by adding inner and outer rings with different diameters. This allows traffic to be routed through shorter paths in the inner ring when possible, reducing transfer latency while maintaining the simplicity of ring-based implementation. The bidirectional capability adds another dimension to the topology without significantly increasing implementation complexity.
Data Source
AI summary
A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption. A back pressure mechanism allows the ring hops on a given communications ring to address overflow conditions on that ring, and a request mechanism allows the ring hops on a given communications ring to request use of that ring to carry a packet communication.