Hysteresis Input Buffer With Gate-Voltage Protection for LDMOS FETs
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Solution Overview
Problem
LDMOS FETs in input buffers have low maximum gate-to-source voltage limitations, making them impractical for high voltage applications, especially in hysteresis input buffers.
Innovation Solution
An input buffer design incorporating a chain of transistors with hysteresis feedback loops and voltage protection devices to prevent maximum gate-to-source voltage violations, using LDMOS FETs in a hybrid region to manage high input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If LDMOS FETs are used in input buffers to reduce area consumption, then area efficiency is improved, but maximum gate-to-source voltage limitation decreases making them impractical for high voltage applications
Solution Approach 1:
The patent introduces voltage protection devices as intermediary elements between the high voltage input buffer and the LDMOS FET gates. These protection devices act as mediators that limit the gate-to-source voltage to safe levels while allowing the LDMOS FETs to operate in high voltage environments, thus resolving the contradiction between area efficiency and voltage reliability
Solution Approach 2:
The voltage protection devices are integrated directly into the input buffer circuitry, allowing the buffer to self-protect against voltage violations without requiring external protection circuits. This self-service approach maintains area efficiency while ensuring voltage reliability
2Reliability
If hysteresis feedback loop is added to input buffer for noise resistance, then noise immunity is improved, but device complexity increases
Solution Approach 1:
The patent merges the hysteresis feedback loop with the voltage protection devices and existing buffer circuitry. By combining multiple functions (hysteresis, voltage protection, and buffering) into an integrated structure, the patent achieves noise resistance while minimizing the increase in device complexity through functional consolidation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents voltage violations, enabling stable operation of LDMOS FETs in high voltage environments by managing gate-to-source voltages within safe limits, ensuring reliable data inversion and noise resistance.
Implementation Method 1
two voltage protection devices, which are connected to gates of the two second transistors, respectively, and to the output node
Implementation Method 2
The input buffer can further include a hysteresis feedback loop. The hysteresis feedback loop can include two second transistors
Data Source
AI summary
Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.