Hysteresis Control Circuits for Programmable Logic Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in effectively mitigating system noise and fluctuations in voltage levels, leading to unreliable input buffer transitions due to the lack of hysteresis control in their input buffers.
Innovation Solution
The implementation of hysteresis control circuits and generators in PLDs, which generate hysteresis control signals and voltages based on core and I/O voltages to adjust trip points of input buffers, thereby reducing noise-induced transitions by applying hysteresis voltages to input buffers on a per-bank basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hysteresis control circuits and generators are implemented in PLDs to adjust trip points of input buffers, then noise-induced transitions are reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The PLD is divided into multiple I/O banks, each with independent hysteresis control circuits and generators. This segmentation allows hysteresis to be applied locally to specific banks that need it, rather than globally to the entire device, reducing overall complexity while maintaining reliability where needed.
Solution Approach 2:
The hysteresis control circuits and generators are designed to be shared across configuration and functional modes. The same circuitry that provides hysteresis during normal operation also functions during configuration, eliminating the need for separate hysteresis control paths and reducing device complexity.
2Object-affected harmful factors
If hysteresis control is applied to all I/O banks, then noise mitigation is maximized, but die size increases
Solution Approach 1:
By dividing the PLD into I/O banks with selective hysteresis control, hysteresis is applied only to banks that require noise mitigation. This selective approach reduces the total die area compared to implementing hysteresis across the entire device, while still providing adequate noise protection where needed.
Solution Approach 2:
Hysteresis control is applied locally to specific I/O banks based on their noise susceptibility requirements rather than uniformly across all banks. This allows critical banks to receive enhanced noise mitigation while non-critical banks use simpler circuits, optimizing the balance between noise protection and die area.
3Adaptability or versatility
If separate hysteresis control circuits are provided for configuration and functional modes, then mode-specific optimization is achieved, but device complexity and die size increase
Solution Approach 1:
The hysteresis control circuits and generators are designed as universal components that operate in both configuration and functional modes. The same circuitry adapts its behavior based on the operational mode, eliminating the need for separate hysteresis control paths for each mode and significantly reducing device complexity.
Solution Approach 2:
The hysteresis control functionality for configuration mode and functional mode is merged into a single integrated circuit structure. By combining these functions, the patent reduces the number of components, simplifies control logic, and decreases die area while maintaining mode-specific optimization capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness of PLDs by reducing system noise-induced transitions and adapting to changes in I/O voltage levels, allowing for die size reduction by sharing hysteresis circuitry across configuration and functional modes.
Implementation Method 1
hysteresis control circuits and generators in PLDs, which generate hysteresis control signals and voltages based on core and I/O voltages to adjust trip points of input buffers, thereby reducing noise-induced transitions by applying hysteresis voltages to input buffers
Data Source
AI summary
Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.