Hysteresis Input Buffer With Gate-Voltage Protection for High-Voltage I/O
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Solution Overview
Problem
Small laterally diffused metal oxide semiconductor (LDMOS) field effect transistors (FETs) used in input buffers have low maximum voltage limitations, making them impractical for high voltage applications with hysteresis due to violations of maximum gate-to-source voltage limitations.
Innovation Solution
An input buffer structure with a chain of transistors and a hysteresis feedback loop, incorporating voltage protection devices to prevent maximum gate-to-source voltage violations, includes two intermediate nodes and an output node, with voltage protection devices connected to the gates of second transistors in the feedback loop to limit gate voltages and prevent source voltage exceedances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If small LDMOS FETs are used in input buffers, then area consumption is reduced, but maximum gate-to-source voltage limitation is lowered making them impractical for high voltage applications
Solution Approach 1:
Voltage protection devices are introduced as intermediary elements between the hysteresis feedback loop and the LDMOS FET gates. These protection devices clamp the gate-to-source voltage to remain within safe limits while allowing the buffer to operate at high input voltages, thus enabling small LDMOS FETs to be used in high voltage applications without exceeding their voltage ratings
Solution Approach 2:
The invention changes the voltage parameters by introducing clamping mechanisms that dynamically control the gate-to-source voltage. The voltage protection devices ensure that even when input voltages are high, the actual voltage across the FET gates remains within the safe operating range, effectively decoupling the input voltage level from the gate-to-source voltage stress
2Adaptability or versatility
If hysteresis feedback loop is implemented with small LDMOS FETs, then input buffer functionality is achieved, but maximum gate-to-source voltage limitations are violated in high voltage applications
Solution Approach 1:
Voltage protection devices serve as intermediary components inserted into the hysteresis feedback path. These devices prevent direct coupling of high voltage swings to the FET gates by clamping the voltage differential, allowing the feedback loop to function while protecting the LDMOS FETs from voltage exceedance
Solution Approach 2:
The voltage protection devices provide beforehand cushioning by pre-establishing voltage clamping mechanisms that prevent gate-to-source voltage from exceeding maximum limits. This protective measure is built into the circuit architecture before voltage violations can occur, ensuring reliable operation in high voltage environments
Data Source
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AI summary
Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.