Hysteresis Latch Circuit for Soft Error Hardening
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Solution Overview
Problem
Logic designs in integrated circuits are increasingly susceptible to single event upsets due to technology scaling, making it difficult to protect flip-flops against soft errors caused by radiation, and existing solutions often incur significant area and performance overhead.
Innovation Solution
A hysteresis-based logic element design is implemented, which increases the switching threshold and critical charge of logic elements by adding secondary cross-coupled inverter pairs, thereby enhancing immunity to soft errors without substantial area or performance penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If technology scaling is applied to reduce critical charge, then device size and power consumption are reduced, but susceptibility to single event upsets increases
Solution Approach 1:
The patent modifies the electrical parameters of the logic element by introducing hysteresis through cross-coupled inverters. This changes the voltage transfer characteristics and switching thresholds, creating a system that maintains low power operation while achieving higher immunity to single event upsets through altered electrical behavior rather than increased device size
Solution Approach 2:
The cross-coupled inverter configuration creates positive feedback loops that establish hysteresis in the logic element. This feedback mechanism ensures that once a switching threshold is crossed, the system remains stable against small perturbations from radiation events, thereby improving reliability without increasing power consumption or device area
2Reliability
If error detection/correction schemes are applied to memory cells, then soft error protection is improved, but device complexity and area overhead increase
Solution Approach 1:
The patent extracts the error protection function from separate error detection/correction circuits and integrates it directly into the logic element itself through hysteresis-based design. This eliminates the need for external ECC schemes, reducing device complexity while maintaining soft error protection
Solution Approach 2:
The hysteresis-based logic element serves multiple functions simultaneously: it performs logic operations, provides soft error protection, and maintains low power consumption. This multi-functionality eliminates the need for separate protection circuits, thereby reducing overall device complexity
3Reliability
If hysteresis-based design is applied to increase switching threshold, then critical charge and soft error immunity are improved, but area overhead increases
Solution Approach 1:
The patent merges the hysteresis functionality directly into the existing logic element structure by adding cross-coupled inverters to the standard cell design. This integration approach achieves improved soft error immunity without requiring separate protection circuits, thereby minimizing area overhead
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hysteresis-based design significantly improves the soft error rate performance while maintaining a low area overhead, effectively increasing the critical charge required to cause upsets, thus reducing the occurrence of soft errors in logic elements.
Implementation Method 1
A hardening technique based on hysteresis can be used to increase the switching threshold and, in turn, the critical charge
Data Source
AI summary
A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.