Hysteretic Comparator Feedback Circuit for Stable Threshold Accuracy
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Solution Overview
Problem
Existing hysteretic comparators face challenges in achieving an accurate and stable hysteresis window without consuming a large IC die area, particularly due to transistor transconductance variations during fabrication and environmental changes, especially in CMOS transistors.
Innovation Solution
A hysteretic comparator design featuring a differential input stage with current output, a steerable offset current generator, and a current-to-voltage summing converter, incorporating feedback resistance to negate transistor transconductance variations and ensure an accurate hysteresis window, with transistors sized to cancel out transconductance differences and minimize die area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistor sizes are increased to improve transconductance matching and reduce hysteresis window variation, then measurement precision of hysteresis window is improved, but IC die area consumption increases
Solution Approach 1:
The patent changes the controlling parameter from transistor transconductance (Gm) to resistor ratio. By using the relationship Vhys = (R1/R2) * Vref, the hysteresis window is determined by resistor ratios rather than transistor Gm values. Resistor ratios can be fabricated with much tighter tolerances (e.g., 0.1%) compared to transistor Gm matching (e.g., 5-10%), achieving accurate hysteresis windows without requiring large transistor sizes.
Solution Approach 2:
The patent substitutes the transistor-based transconductance control mechanism with a resistor-based voltage division mechanism. Instead of relying on the transconductance of differential input transistors to set the hysteresis window, the invention uses a resistive divider network (R1, R2) connected to a reference voltage (Vref) to generate the hysteresis control voltage, replacing the mechanical/electrical property of transistor Gm with a more stable resistive property.
2Reliability
If transistor sizes are increased to improve transconductance matching, then hysteresis window stability against environmental variations is improved, but IC die area consumption increases
Solution Approach 1:
The patent changes the physical parameter used to define the hysteresis window from transistor transconductance (which varies with temperature and process) to resistor ratios and reference voltage. Resistors exhibit much better temperature stability and process matching than transistors, and the reference voltage can be designed to be temperature-compensated, thereby improving hysteresis window stability without increasing device size.
Solution Approach 2:
The patent replaces the temperature-sensitive transistor transconductance mechanism with a temperature-stable resistive voltage division mechanism. The resistive divider (R1, R2) combined with Vref creates a hysteresis control voltage that is insensitive to temperature variations, eliminating the need for large oversized transistors to achieve thermal stability.
3Manufacturing precision
If transistor transconductance is increased to reduce sensitivity to fabrication variations, then manufacturing precision of hysteresis window is improved, but IC die area consumption increases
Solution Approach 1:
The patent changes the fabrication-critical parameter from transistor dimensions (which have poor matching due to process variations) to resistor ratios. Modern CMOS fabrication processes can achieve resistor ratios with 0.1% or better matching, whereas transistor Gm matching typically achieves only 5-10% even with careful design. This parameter change enables high manufacturing precision for the hysteresis window using standard-sized components.
Solution Approach 2:
The patent substitutes the transistor transconductance-setting mechanism with a resistive voltage division mechanism. The hysteresis window is set by the ratio R1/R2 and the reference voltage Vref, both of which can be fabricated with high precision using standard CMOS processes. This eliminates the need to oversize transistors to achieve acceptable Gm matching, thereby reducing IC die area while improving manufacturing precision.
Data Source
AI summary
A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window Vhys. The hysteretic comparator includes a differential input stage with current output (DICO) having input transistors with transconductance Gmtnx for converting the input signals, with an input stage transconductance Gmin, into intermediate signal currents. A steerable offset current generator, driven by a steering control signal, steers an offset current source IOS to alternative offset currents. A current-to-voltage summing converter (IVSC) sums up the intermediate signal currents and the offset currents and converts the result into VOT plus the steering control signal causing Vhys=IOS/Gmin. A feedback resistance RNF is connected to the input transistors to form a negative feedback loop. The RNF is sized such that GMin, hence Vhys, becomes essentially solely dependent upon the feedback conductance GNF=1/RNF independent of the Gmtnx thus its process and environmental variation.