Hysteretic Converter Controller Asynchronous Clock Ripple Reduction
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Solution Overview
Problem
Hysteretic boost or buck-boost converters experience significant output voltage ripple due to variable load conditions and small output capacitors, leading to inefficiencies and increased ripple variability.
Innovation Solution
A controller is developed that generates asynchronous clock pulses based on the difference between the feedback voltage and a reference voltage, using a clock generating circuit and pulse width modulation to synchronize the switch activation, reducing the output voltage ripple by eliminating or fixing delay td1 and modulating pulse width accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed duty cycle and fixed frequency clock pulse is used to control the FET, then the converter design is simple, but the output voltage ripple varies significantly with load conditions
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed frequency clock pulse to an asynchronous clock pulse whose frequency dynamically adjusts based on the difference between feedback voltage and reference voltage. The control circuit generates clock pulses asynchronously, allowing the switching frequency to vary with load conditions, thereby stabilizing output voltage ripple across different operating points while maintaining relatively simple converter architecture.
2Device complexity
If the clock pulse frequency is fixed, then the control circuit is simple, but there is a variable delay td1 between when output voltage drops below reference voltage and when the next gate pulse is initiated
Solution Approach 1:
The patent implements feedback by using the output voltage (feedback voltage) to control the clock pulse generation. The control circuit continuously monitors the feedback voltage and compares it with the reference voltage, generating clock pulses asynchronously based on this comparison. This feedback mechanism eliminates the variable delay td1 by ensuring the next gate pulse is initiated immediately when the output voltage drops below the reference voltage, rather than waiting for the next fixed frequency cycle.
3Volume of stationary object
If a small output capacitor is used, then the converter size is reduced, but the output voltage ripple becomes large and highly variable
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the switching frequency (clock pulse frequency) based on operating conditions. Instead of using a large output capacitor to reduce ripple, the system changes the frequency parameter of the switching converter to adapt to load variations. This allows the use of smaller output capacitors while maintaining stable output voltage ripple through frequency modulation rather than capacitance.
Data Source
AI summary
An apparatus and method for reducing an output voltage ripple of a converter are provided. The apparatus may include a controller for controlling a converter, wherein the controller may include a clock generating circuit that generates a periodic clock signal containing periodic clock pulses, and a control circuit that causes the clock generating circuit to asynchronously initiate a clock pulse based on a difference between a feedback voltage of the converter and a reference voltage. The apparatus may also include an on-time modulation circuit which modulates the on-time based on the difference between the reference voltage and the sampled output voltage.