HZO Capacitor Stack for Scaled DRAM Capacitance Retention
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Solution Overview
Problem
The challenge in advanced memory technology is scaling down capacitor dielectric materials while maintaining sufficient capacitance, as current material stacks face limitations in leakage and capacitance, particularly in dynamic random access memory (DRAM) devices.
Innovation Solution
A method of forming a capacitor structure involving a hafnium-zirconium oxide (HZO) layer and an interface dielectric layer, where the HZO layer is formed using thermal or plasma atomic layer deposition processes, and the layers are annealed to enhance the tetragonal crystal phase concentration, thereby increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If capacitor dielectric materials are scaled down to meet smaller transistor sizes, then device integration density is improved, but capacitance sufficiency deteriorates
Solution Approach 1:
The patent employs a composite dielectric structure consisting of HZO layer and interface dielectric layer. The HZO layer provides high capacitance density while the interface dielectric layer ensures proper electrical characteristics, together achieving sufficient capacitance in scaled-down capacitors
Solution Approach 2:
The patent optimizes the thickness of the HZO layer (4-6 nm) and controls the annealing temperature to enhance the tetragonal crystal phase concentration. By adjusting these parameters, the dielectric performance is improved to maintain sufficient capacitance in scaled capacitors
2Ease of manufacture
If current material stacks are used for capacitor scaling, then manufacturing process is simple, but leakage and capacitance performance deteriorate
Solution Approach 1:
The patent replaces current material stacks with a composite HZO and interface dielectric layer structure. This composite structure addresses leakage and capacitance performance issues while maintaining compatibility with existing manufacturing processes through ALD deposition and annealing
3Stability of the object's composition
If HZO layer is formed at low temperature to preserve material properties, then material integrity is improved, but interface dielectric layer formation quality deteriorates
Solution Approach 1:
The patent separates the formation process into two distinct temperature stages: HZO layer formation at low temperature (25-300°C) to preserve material integrity, followed by interface dielectric layer formation at higher temperature (300-350°C) to ensure proper interface quality and tetragonal phase concentration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for the formation of capacitors with improved dielectric performance, enabling sufficient capacitance and scalability for small transistor sizes in DRAM structures, addressing the limitations of existing material stacks.
Implementation Method 1
The HZO layer and the interface dielectric layer are annealed
Implementation Method 2
enhance the tetragonal crystal phase concentration
Implementation Method 3
the hafnium oxide layers and the zirconium oxide layers are further mixed under the second temperature when the interface dielectric layer is formed under the second temperature
Data Source
AI summary
A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.