I2C Address Decoder Using Shared Bus Lines for Module Addressing
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Solution Overview
Problem
Existing techniques for setting addresses in I2C communication systems are not versatile and are affected by manufacturing variations, making them unsuitable for integration, especially when a large number of modules need to be connected to a bus line with limited terminal availability.
Innovation Solution
An address decoder that uses a signal intensity comparator, edge detector, and output decoder to set addresses based on a reference serial data signal and an address selection signal formed by power supply, ground, or serial data signals, allowing for efficient address determination even with a small number of terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If digital input terminals are used for address setting, then address setting is simple, but the number of terminals must be increased
Solution Approach 1:
The ADDR terminal is designed to serve multiple functions: it can detect connection to VDD line (power supply), VSS line (ground), SDA line (serial data), or SCL line (serial clock). This multi-functionality allows the single terminal to provide 4 different address settings (0x00, 0x01, 0x02, 0x03) without requiring multiple dedicated address input terminals, thus resolving the contradiction between ease of operation and terminal quantity.
2Adaptability or versatility
If many modules are connected to increase touch keys, then product functionality is improved, but terminal availability becomes limited
Solution Approach 1:
The ADDR terminal detects which line it is connected to (VDD, VSS, SDA, or SCL) and uses this information to set the module address. This allows up to 4 modules to share the same physical terminal while maintaining unique addresses, enabling more modules to be connected without proportionally increasing terminal availability requirements.
Solution Approach 2:
The address decoder circuit acts as an intermediary that translates the physical connection state of the ADDR terminal into logical address values. By detecting the voltage level and signal characteristics, the decoder mediates between the limited physical terminal and the need for multiple unique addresses, allowing more modules to be connected.
3Measurement precision
If existing address setting techniques are used, then address detection is possible, but the techniques are not versatile and are affected by manufacturing variations
Solution Approach 1:
The address setting mechanism works across different I2C protocol versions and implementations by detecting fundamental electrical characteristics (voltage levels, signal presence) rather than relying on protocol-specific timing or sequences. This makes the solution versatile and protocol-independent while maintaining accurate address detection through robust electrical signal comparison.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables easy and efficient address setting for multiple modules connected to a bus line, ensuring reliable communication by accurately determining addresses using a simple circuit structure and reducing the need for additional terminals.
Implementation Method 1
a signal level comparator for comparing the serial data signal with the address selection signal and outputting a comparison result
Data Source
AI summary
An address decoder that sets an address of a module connected to a bus includes a level comparator, an edge detector, and an output decoder. The level comparator compares an SDA signal, which is input to an SDA terminal, with an address selection signal, which is input to an ADDR terminal, and outputs a comparison result. When the two signals match, the comparison is repeated until slave addresses are all received. When the two signals do not match, subsequent comparisons are not performed. The edge detector detects an edge of the address selection signal input to the ADDR terminal. The output decoder sets an address corresponding to the connected destination of the ADDR terminal to determine an address of a slave module connected to the address decoder.