I2C Bus Analog Addressing for Slave Multiplexing
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Solution Overview
Problem
The existing I2C bus system is limited in the number of slave devices that can be connected due to address constraints and total capacity limitations, making it difficult to connect multiple slave devices with the same address or exceed the specified capacity.
Innovation Solution
The proposed I2C bus system uses an analog addressing signal line to transmit a range-defined addressing signal, allowing multiple slaves with the same I2C address to be connected by attributing a specific range to each slave, and enabling/disabling connections based on the signal being within the attributed range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple slave devices with the same I2C address are connected to a common I2C bus, then the number of connectable slave devices is increased, but the I2C specification limits the number of slave devices and requires unique addresses
Solution Approach 1:
The patent divides the addressing function into two independent parts: the digital I2C address (7-bit or 10-bit) and the analog addressing signal voltage level. Each slave device is assigned a specific voltage range (e.g., 0-0.6V, 0.6-1.2V, 1.2-1.8V) corresponding to its position on the bus. This segmentation allows multiple devices with the same I2C address to be distinguished by their analog voltage levels, effectively multiplying the addressable devices while maintaining address uniqueness within each voltage segment.
Solution Approach 2:
The patent introduces an analog addressing signal as an intermediary between the master and slave devices. This analog signal acts as a mediator that carries position information without interfering with the digital I2C communication protocol. The master device sends both the digital I2C address and the analog voltage signal simultaneously, and slave devices use the analog signal to determine whether to respond to the digital address, thus enabling multiple devices with the same address to coexist on the bus.
2Quantity of substance
If an I2C bus switch or multiplexer is used to enable multiple slaves, then the number of addressable slaves is increased, but the master position is fixed and PCB design becomes more complicated
Solution Approach 1:
The patent extracts the address selection function from the digital I2C address space and relocates it to the analog voltage domain. Instead of using complex switching matrices or multiplexers to manage address assignments, each slave device independently generates its own analog voltage signature based on its position. This extraction eliminates the need for complex PCB routing and switching control logic, simplifying the overall system design while maintaining the capability to address multiple slaves.
Solution Approach 2:
Each slave device autonomously determines its addressability by comparing the received analog addressing signal with its predefined voltage range. The slave devices self-configure their response behavior based on the analog voltage level without requiring external control logic or complex PCB design. This self-service mechanism eliminates the need for master-controlled switching and simplifies the PCB layout to basic analog signal distribution.
3Quantity of substance
If an I2C address translator is used to translate addresses, then multiple slaves can be addressed, but the master position is fixed and PCB design becomes more complex
Solution Approach 1:
The patent makes the addressing system dynamic by allowing the analog voltage signature to change based on the slave device's position on the bus. Instead of fixed address translations, each slave device dynamically asserts its presence by matching the analog voltage level corresponding to its physical position. The master device can operate from any position on the bus, and the analog voltage signaling automatically adapts to the physical layout, providing flexibility in master positioning while enabling multiple slaves to be addressed.
Data Source
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AI summary
An I2C bus system (1) comprises a data bus (8), a clock bus (9) and an addressing signal line (10) for connecting a master (4) and a plurality of slaves (5n), wherein the addressing signal line (10) is configured to transmit an analog addressing signal (AS) from the master (4) to the slaves (5n), wherein to each of the slaves (5n) a range of the analog addressing signal (AS) is attributed, the range being defined by a high threshold level (HT) and a low threshold level (LT), wherein the I2C bus system (1) is configured to selectively connect each of the slaves (5n) to the data bus (8) and clock bus (9) only if the addressing signal is in the range.