I2C Bridge Device Address Translation and Clock Stretching
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Solution Overview
Problem
The I2C protocol faces limitations such as limited address space, voltage level incompatibility, and communication speed constraints, leading to issues with device compatibility and communication efficiency, particularly when multiple devices with different voltage levels and clock frequencies are connected to the same bus.
Innovation Solution
A transparent bridge device is introduced, operating between a parent I2C bus and a child I2C bus, allowing for message translation and clock stretching to ensure reliable communication without requiring modifications to master or slave devices, and enabling multiple child I2C buses to be connected with address translation and voltage compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple devices with different voltage levels are connected to the same I2C bus, then device compatibility is improved, but voltage level incompatibility causes communication failures
Solution Approach 1:
The patent introduces a voltage level translator as an intermediary device between I2C devices operating at different voltage levels. The translator converts voltage levels between domains, allowing a 3.3V I2C bus to communicate with 1.8V I2C devices without modification to the original devices, thus resolving the voltage incompatibility while maintaining communication reliability
2Reliability
If the I2C bus operates at the lowest supported speed of all devices, then all devices can interpret communication correctly, but communication efficiency deteriorates
Solution Approach 1:
The patent segments the I2C bus into multiple domains with different speed capabilities. Fast-mode devices (supporting 400kHz) can operate at higher speeds on their own segment, while slow-mode devices (supporting only 100kHz) operate at lower speeds on their segment. The system arbitrates between segments, allowing fast transfers when only fast devices are involved, thus improving overall communication efficiency without sacrificing correctness for slow devices
3Ease of operation
If 7-bit address space is used in I2C protocol, then device addressing is simplified, but address collisions occur when multiple devices share the same address
Solution Approach 1:
The patent extends the I2C address space by utilizing the R/W bit (normally used for read/write direction) as an additional address bit. This allows 10-bit addressing capability while maintaining compatibility with existing 7-bit addressing schemes. Devices can be addressed with up to 10 bits, effectively quadrupling the addressable device count from 127 to over 1000 devices, thus resolving address collisions without complicating the basic addressing mechanism
4Adaptability or versatility
If a transparent bridge device is introduced to enable communication between different I2C domains, then device compatibility is improved, but device complexity increases
Solution Approach 1:
The patent designs the bridge device to perform multiple functions within a single integrated component: voltage level translation, speed domain adaptation, and address space extension. By combining these functions into one universal bridge, the system avoids the need for separate translation devices for each function, thereby reducing overall system complexity while maintaining full compatibility between different I2C domains
Data Source
AI summary
The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arranged for translating an I2C event to a message and for forwarding said message to the module at the other side of the bridge device via said internal bridge interfaces, said module at the other side being arranged for further transmitting said message as an I2C event towards the I2C bus at the other side of the bridge device, and whereby said parent module and said child module are further each arranged for holding the communication towards the respective I2C bus by stretching a clock line on their respective I2C bus until a message, based on an event occurring on the I2C bus at the other side of the bridge device and instructing continuation of the communication, is received via said internal bridge interfaces from the module at the other side of the bridge device.