I2C Bus Pin Reduction via Power Control Manager
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Solution Overview
Problem
In applications using serial buses like the I2C bus, the limited pin count poses a challenge as slave units require additional pins for power and control, increasing resource usage and complexity.
Innovation Solution
A power control manager is implemented to utilize a signal line for both power and control, eliminating the need for dedicated power and control pins by coupling the signal line to a bus power supply through current limiting devices, allowing the slave unit to derive power from the bus signals during quiescent periods and store it for active periods, thus reducing pin requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated power and control pins are added to the slave unit, then power and control functions are improved, but pin count increases
Solution Approach 1:
The patent combines power and control functions with data communication by utilizing the existing I2C bus signal lines. The slave unit's power control manager uses the SDA and SCL lines not only for data communication but also for deriving power during quiescent periods, thereby eliminating the need for separate power and control pins while maintaining all necessary functions.
Solution Approach 2:
The I2C bus signal lines are made multi-functional by enabling them to serve both as communication channels and power sources. The power control manager detects bus states and selectively uses the signal lines for power derivation during quiescent periods and for communication during active periods, allowing one component to perform multiple functions.
2Reliability
If additional wiring is provided for power and control pins, then power and control delivery are improved, but device complexity increases
Solution Approach 1:
The patent merges power delivery and control functions into the existing communication bus infrastructure. By using the I2C bus signal lines for both communication and power/control purposes, the patent eliminates the need for additional wiring, thereby reducing device complexity while maintaining reliable power and control delivery through the shared bus lines.
3Quantity of substance
If signal lines are used for both power and control, then pin requirements are reduced, but power management complexity increases
Solution Approach 1:
The power control manager autonomously monitors the I2C bus state and automatically switches between power derivation mode and communication mode without external intervention. The system self-manages the complex power management tasks by detecting bus activity and selectively coupling or decoupling the capacitor from the signal lines, thereby reducing pin requirements while keeping the power management complexity internal to the device.
4Quantity of substance
If power is derived from bus signals during quiescent periods, then pin count is reduced, but power availability during active periods must be maintained
Solution Approach 1:
The patent implements preliminary action by charging the capacitor during quiescent periods when the bus is inactive. This stored energy in the capacitor is then available to power the slave unit during active communication periods, ensuring continuous power availability without requiring additional pins. The system proactively accumulates energy in advance of when it will be needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces pin requirements, eliminates unnecessary wiring, and allows for controlled power management without affecting normal bus operation, enabling more efficient use of resources and simplified pin configurations.
Implementation Method 1
A slave unit is coupled to the bus and is arranged to couple power from the first (and/or second) signal line to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus.
Data Source
AI summary
A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit is coupled to the bus and is arranged to transmit communications across the bus during an active period of the bus and to initiate communications during (and/or at the end of) a quiescent period of the bus. A slave unit is coupled to the bus and is arranged to couple power from the one or more signal lines to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus.