I2C Bus Rapid Switching via Simplified Signaling Protocol
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Solution Overview
Problem
The Inter-Integrated Circuit (I2C) bus technology is limited by slow transaction speeds, which hinder applications with repetitive or predictable tasks, as the existing arbitration process and open-drain technology restrict flexibility and speed, particularly in scenarios requiring rapid data exchange.
Innovation Solution
A method and apparatus that enable rapid transactions over a speed-limited bus by pre-loading parameters, enabling a simplified signaling protocol, and switching between dedicated hardware configurations, utilizing a Hardware Gain Switching Mode (HGSM) that allows for efficient operation on the I2C bus by reducing unnecessary signaling overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the standard I2C bus protocol with arbitration process is used, then device flexibility and protocol compatibility are maintained, but transaction speed is limited and slow
Solution Approach 1:
The patent segments the I2C bus operation into two distinct modes: standard I2C mode for general communication and a simplified rapid transaction mode for high-speed operations. This segmentation allows the system to use the appropriate protocol for each task type, achieving high speed when needed while maintaining standard compatibility for other operations.
Solution Approach 2:
The patent implements dynamic protocol switching capability, allowing the I2C bus to transition between standard and simplified signaling protocols based on operational requirements. This dynamic adaptation enables the system to optimize transaction speed for repetitive tasks while maintaining compatibility for other operations.
2Speed
If the open-drain technology with arbitration process is used, then multi-master capability and device independence are achieved, but transaction speed is restricted
Solution Approach 1:
The patent applies partial action by implementing a simplified protocol that disables certain I2C features (arbitration, multi-master capability) when they are not needed for the specific task. This allows the system to achieve maximum speed for repetitive single-master operations while retaining full multi-master capability when required.
Solution Approach 2:
The patent changes the operational parameters of the I2C bus by switching between different signaling protocols. The simplified protocol uses different timing parameters and signaling levels optimized for high-speed single-master operations, while the standard protocol maintains original parameters for multi-master compatibility.
3Productivity
If a simplified signaling protocol is used for rapid transactions, then transaction speed is enhanced, but protocol flexibility and standard capabilities are reduced
Solution Approach 1:
The patent implements periodic switching between standard and simplified protocols based on task requirements. Repetitive tasks use the simplified protocol for high efficiency, while tasks requiring standard I2C features switch to the standard protocol, creating a periodic pattern of protocol usage optimized for different operational phases.
Solution Approach 2:
The patent creates a universal communication framework that supports both standard I2C operations and rapid transactions through a single bus interface. The system can perform multiple functions using the appropriate protocol for each function, making the I2C bus universally applicable for both speed-critical and compatibility-critical operations.
Data Source
AI summary
Methods and apparatus for enabling rapid transactions over a speed limited bus are disclosed. In one exemplary embodiment of the present disclosure, a host controller and an application specific integrated circuit (ASIC) are connected via an Inter-Integrated Circuit (I2C) Bus that is further adapted to enable a simplified signaling scheme. Unlike traditional I2C bus transactions which are flexible but speed limited, the simplified signaling scheme reduces bus overhead and enables rapid transactions. In an exemplary context, the simplified signaling scheme enables the ASIC to rapidly configure a series of photodiodes with different channel gain parameters so as to, for example, measure heartbeats by visually detecting a pulse within human flesh.