I2C Bus Data Rate Doubling via Clock Line Encoding

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Solution Overview

Problem

The Inter-Integrated Circuit (I2C) data communications interface struggles to achieve its theoretical bandwidth due to the use of passive drivers that often fail to meet rise time requirements, resulting in bus frequencies lower than the maximum possible speed.

Innovation Solution

The method involves transmitting an SDL data signal and an SCL data signal in parallel, where the SCL signal is encoded with bits having rise times less than or not less than a predefined threshold to represent different binary values, effectively doubling the data rate by utilizing the clock line as a data line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If passive drivers are used in I2C interface, then device complexity is reduced, but data transmission rate decreases below theoretical bandwidth

Engineering Contradiction:
Improvedata transmission rateVSAvoiddriver complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the parameter being used for data encoding from amplitude/voltage level alone to include rise time characteristics. By encoding data in the rise time parameter of clock transitions (fast rise time for one binary value, slow rise time for another), the system achieves higher data transmission rates without changing the fundamental passive driver architecture or increasing bus frequency.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If bus frequency is increased to achieve higher bandwidth, then data transmission rate improves, but compatibility with I2C standard decreases

Engineering Contradiction:
Improvedata transmission rateVSAvoidI2C standard compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

Instead of increasing data transmission rate by moving to a higher dimension (increasing bus frequency), the patent exploits an underutilized dimension within the existing clock signal - the rise time characteristic of clock transitions. This allows encoding additional data bits in the temporal characteristic of the same frequency signal, effectively doubling the data rate while maintaining I2C standard compatibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If passive drivers are used, then ease of manufacture is improved, but rise time requirements are not met

Engineering Contradiction:
Improveinterface implementation easeVSAvoidrise time specification compliance
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes which parameter is used for data encoding - from relying on precise voltage rise times to utilizing rise time as an encoding dimension itself. This approach works well with passive drivers because it doesn't require them to meet stringent rise time specifications; instead, the rise time characteristics become part of the data encoding scheme, maintaining ease of manufacture while achieving higher data rates.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9098645B2Increasing data transmission rate in an inter-integrated circuit (‘I<sup>2</sup>C’) system
Publication Date: 2015.08.04 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US9098645B2 patent drawing
  • US9098645B2 patent drawing
  • US9098645B2 patent drawing

AI summary

Increasing data transmission rate in an I2C system that includes an I2C source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.