Master-Slave I2C Clock Stretching Wait Time
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Solution Overview
Problem
Existing I2C communication systems face challenges in balancing immediate data readout, low power consumption, cost-effectiveness of slave ICs, and increased bandwidth, particularly when dealing with sensors that may not be ready to provide data immediately.
Innovation Solution
The proposed electronic system includes a master IC and a slave IC connected via a serial communication interface with a bidirectional data line and a clock line. The master IC sends a data request command, followed by a data read command after a measured wait time based on the duration of clock stretching by the slave IC, which deactivates the clock line until data is available.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the master IC sends a data read command immediately after a data request command, then immediate data readout is achieved, but the slave IC may not be ready to provide data causing communication failures
Solution Approach 1:
The master IC sends a data request command in advance to trigger the slave IC to prepare the requested data before the actual read operation. This preliminary action allows the slave IC to start data preparation early, ensuring data readiness when the read command arrives.
Solution Approach 2:
The slave IC provides feedback by deactivating the clock line to signal when it is not yet ready to provide data. The master IC monitors this clock line deactivation and adjusts its timing accordingly, creating a feedback mechanism that ensures reliable communication.
2Reliability
If the master IC waits for a long time before sending a data read command, then the slave IC is guaranteed to be ready, but data readout is delayed and bandwidth is reduced
Solution Approach 1:
By sending the data request command in advance, the slave IC is given time to prepare data without requiring the master IC to wait unnecessarily long. This optimization allows the system to achieve both data reliability and higher bandwidth by eliminating excessive wait times.
3Speed
If additional interrupt pins are added to the slave IC to signal data readiness, then immediate data readout is enabled, but the cost and complexity of the slave IC increases
Solution Approach 1:
The clock line serves as an intermediary mechanism between the master IC and slave IC for signaling data readiness. Instead of adding dedicated interrupt pins, the existing clock line is used to convey readiness information through deactivation, maintaining simplicity while enabling fast data readout.
4Reliability
If the system uses continuous polling to check data availability, then data readiness is monitored, but power consumption increases
Solution Approach 1:
Instead of continuous polling, the system uses periodic action where the slave IC intermittently deactivates the clock line to signal data readiness. The master IC monitors these periodic deactivations rather than continuously checking, significantly reducing power consumption while maintaining reliable data availability monitoring.
Data Source
AI summary
The present disclosure relates to an electronic system including a master IC, a slave IC and a serial communication interface having a bidirectional data line and a clock line. The master IC is configured to send a data request command to the slave IC via the data line. The slave IC is configured to begin providing requested data in response to the data request command. The slave IC is configured to deactivate the clock line after receiving a data read command and until the slave IC can provide the requested data. The master IC is configured to measure a duration of the deactivation of the clock line and to set a wait time between a next data request command and a next data read command according to the measured duration.