I2C Bus Control Circuit Continuous Transmission Interrupt Handling
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Solution Overview
Problem
Conventional I2C bus control circuits experience increased transmission time due to interrupt processing overhead, which affects the performance of electronic equipment, especially in high-speed communication scenarios and applications with extensive data transmission like audio visual devices.
Innovation Solution
Incorporating a continuous transmission function in the I2C bus control circuit that generates a first interrupt signal after each byte transmission and disables subsequent interrupt signals, allowing a second interrupt signal to be sent only after completing a designated number of transmissions, thereby reducing the number of interrupt processing events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt processing is performed after each byte transmission in conventional I2C bus control, then data transmission reliability is ensured, but transmission time increases due to interrupt processing overhead
Solution Approach 1:
The patent segments the interrupt processing function into two parts: a lightweight first interrupt signal that triggers continuous transmission mode, and a second interrupt signal that handles final completion. This segmentation allows the system to avoid repeated full interrupt processing cycles while maintaining reliability through staged acknowledgment.
Solution Approach 2:
The patent implements preliminary action by setting up continuous transmission mode in advance. The controller pre-configures the I2C bus control circuit to suppress intermediate interrupt signals, establishing a state where multiple bytes can be transmitted without repeated interrupt handling overhead, thus reducing total transmission time while maintaining reliability.
2Measurement precision
If interrupt signals are generated after every byte transmission, then transmission status monitoring is accurate, but processing speed decreases due to frequent interrupt handling
Solution Approach 1:
The patent applies partial action by providing only the necessary interrupt signals for status monitoring. Instead of generating full interrupt processing events after every byte, the system generates a simplified first interrupt signal that acknowledges transmission completion without triggering full interrupt handling, thus maintaining monitoring accuracy while improving processing speed.
Solution Approach 2:
The patent implements dynamics by making the interrupt signal generation adaptive. The I2C bus control circuit dynamically adjusts interrupt behavior based on transmission state: generating first interrupt signals for status acknowledgment during continuous transmission, and suppressing intermediate interrupts to improve throughput, while still providing second interrupt signals for final completion notification.
3Productivity
If continuous transmission mode is implemented by suppressing interrupt signals, then transmission efficiency improves, but control complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism - the first interrupt signal - that acts as a lightweight acknowledgment without triggering full interrupt processing. This intermediary allows the system to maintain simplified control during continuous transmission while still providing necessary status feedback, thus improving efficiency without significantly increasing control complexity.
Solution Approach 2:
The I2C bus control circuit performs self-service by automatically managing the suppression and generation of interrupt signals based on its internal state. The circuit autonomously determines when to generate first interrupt signals for continuous transmission mode and when to generate second interrupt signals for completion, reducing the burden on the controller and simplifying overall control while maintaining high transmission efficiency.
Data Source
AI summary
An I2C bus control circuit includes a continuous transmission control section in addition to a transmission control section, a sequence control section, a data line control section, and a clock line control section. The continuous transmission control section has a number-of-continuous transmission bytes register and first to (n−1)th continuous transmission data registers, and supplies an interrupt signal to the controller when continuous transmission is completed or an error is detected. The number of times the controller conducts interrupt processing is thus reduced and the processing time is reduced.