I2C Controller Reset Sequence for Optical Transceivers
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Solution Overview
Problem
In optical transceivers using the I2C bus, external RESET signals can cause communication disruptions, leading to persistent SDA LOW states, preventing the controller from controlling circuit units and initiating communication.
Innovation Solution
The controller receives an external RESET, completes communication on the I2C bus, and then sends an internal RESET to circuit units, ensuring secure resumption of communication by setting SCL and SDA to HIGH.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller receives external RESET during I2C communication, then the circuit unit can be reset, but the SDA line remains LOW and communication cannot be resumed
Solution Approach 1:
The controller detects the external RESET signal and completes the current I2C communication transaction before asserting the internal RESET to the circuit unit. This preliminary completion of communication ensures that SDA is released from LOW state before RESET is applied, preventing the communication lockup condition while still achieving the desired circuit unit reset.
2Reliability
If the controller asserts internal RESET to circuit unit, then the circuit unit is reset, but SDA remains LOW preventing START flag generation
Solution Approach 1:
The controller performs the action of completing the current I2C communication transaction before asserting the internal RESET signal to the circuit unit. This ensures that the SDA line is properly released from the LOW state before RESET is applied, preventing the communication lockup while achieving reliable circuit unit reset.
Solution Approach 2:
The reset operation is segmented into two distinct phases: first completing the current communication transaction, then asserting the internal RESET. This segmentation separates the communication completion function from the reset function, allowing each to be executed in the proper sequence without interference.
Data Source
AI summary
An electronic apparatus is disclosed where the apparatus provides the I2C bus and enables to resume the I2C bus even after the apparatus receives external RESET independent of the status of the I2C communication. A circuit unit communicating with the controller by the I2C bus, which is necessary to be reset, is further coupled with the controller by an internal RESET. The controller, receiving the external RESET, first completes the communication on the I2C bus, then sends the internal RESET to the circuit unit, finally resets itself.


