Cross-Coupled I2C Bus Filtering for Spike-Safe Start Detection
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Solution Overview
Problem
Conventional Inter-Integrated Circuit (I2C) systems face issues with synchronization between serial data and clock signals due to transient spikes or glitches, leading to false start conditions and improper operation.
Innovation Solution
The proposed solution involves a deglitch filtering system for I2C buses, comprising SDA and SCL filters with cross-coupled hold and disable terminals, utilizing D flip-flops, multiplexers, and XOR gates to detect and manage transients, ensuring synchronized data and clock signals by issuing disable signals when glitches are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deglitch filters are used for each of SDA and SCL signals, then transient spikes can be filtered, but synchronization between SDA and SCL is lost leading to false start conditions
Solution Approach 1:
The patent merges the filtering operations for SDA and SCL signals into a single synchronized filter unit. The filter receives both signals simultaneously and processes them through shared logic elements (XOR gates, flip-flops) that maintain temporal relationships. This combining approach ensures that transient filtering does not desynchronize the signals, resolving the contradiction between reliable spike filtering and precise synchronization maintenance.
Solution Approach 2:
The filter incorporates feedback mechanisms where the filtered SDA and SCL signals are monitored to detect false start conditions. When transients are detected, the feedback logic generates disable signals that prevent false start detection. This feedback loop ensures that transient filtering maintains signal synchronization by actively correcting synchronization errors, thus resolving the contradiction between filtering reliability and synchronization precision.
2Ease of manufacture
If independent filters are used for SDA and SCL signals, then each signal can be filtered separately, but false start errors occur due to phase misalignment
Solution Approach 1:
Instead of implementing separate independent filters for SDA and SCL, the patent merges them into a unified filter structure that processes both signals together. This unified approach maintains phase alignment while still providing effective transient filtering. The merged design achieves both manufacturing simplicity (single filter unit) and operational reliability (no phase misalignment), resolving the contradiction between ease of manufacture and operation accuracy.
3Reliability
If transient detection is implemented in both SDA and SCL filters, then glitches can be blocked, but system complexity increases due to cross-coupled logic
Solution Approach 1:
The patent merges the transient detection logic for SDA and SCL into a shared detection mechanism within the unified filter. Instead of implementing separate detection circuits, the same XOR gates and flip-flops detect transients in both signals simultaneously. This shared detection approach maintains strong glitch rejection capability while significantly reducing circuit complexity compared to independent detection systems, resolving the contradiction between reliability and device complexity.
Data Source
AI summary
An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter. The I2C interface logic is coupled to the SDA filter and to the SCL filter, and operational circuitry is coupled the I2C interface logic.