I2C EEPROM Addressing for Multiple Device Identification
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Solution Overview
Problem
Current 4-Mbit EEPROM memories cannot be identified by their assignment codes, and only one such memory can be connected to an I2C bus, limiting storage capacity and compatibility with high-density memory systems.
Innovation Solution
A method for addressing non-volatile memory integrated circuits on an I2C bus using J hardware-identification pins, allowing for two modes of addressing: one compatible with existing systems and another that enables multiple 4-Mbit EEPROM memories to be connected to the same bus by using the last three low-order bits of the slave address for identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the standard I2C addressing method is used for 4-Mbit EEPROM memories, then the memory can be addressed with a 19-bit address, but only one such memory can be connected to the I2C bus
Solution Approach 1:
The patent segments the addressing function by separating device identification from memory location addressing. The slave address is divided into two parts: the first 3 bits identify the specific 4-Mbit EEPROM device among multiple devices, while the remaining bits address memory locations within the selected device. This segmentation allows multiple memories to coexist on the same bus.
Solution Approach 2:
The patent introduces an intermediary addressing mechanism where the slave address acts as a mediator between the master device and multiple slave memories. The address structure includes a device identification field that routes communication to the correct memory device, enabling multiple memories to be addressed through a unified I2C interface.
2Quantity of substance
If multiple 4-Mbit EEPROM memories are connected to the same I2C bus, then storage capacity increases, but the memories cannot be identified by assignment codes
Solution Approach 1:
The patent adds another dimension to the addressing space by utilizing the slave address bits that would traditionally be used for memory location addressing. Instead, these bits are repurposed to identify specific memory devices on the bus, creating an additional layer of addressing that enables device differentiation without requiring hardware identification pins.
3Adaptability or versatility
If the slave address is used for memory addressing, then existing I2C systems remain compatible, but no device identification is possible
Solution Approach 1:
The patent makes the slave address universal by enabling it to serve dual functions: device identification and memory location addressing. The address structure is designed so that the same I2C interface and protocol can address both the specific memory device and the location within that device, eliminating the need for separate identification mechanisms while maintaining compatibility with existing systems.
Data Source
AI summary
Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.