I2C Protocol Flash Memory Mode Bit Control
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Solution Overview
Problem
The conventional I2C protocol cannot discern different operations such as program, sector erase, block erase, and chip erase, and read operations in flash memory devices, limiting the ability to control these operations effectively.
Innovation Solution
Incorporating additional bits in the I2C protocol to indicate the mode of operation, allowing the processor and memory device to transmit and receive messages that include a start bit, address bits, a read/write bit, and a mode operation bit, enabling the control of flash memory devices to perform specific operations like programming, erasing, and reading at various speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the conventional I2C protocol is used for communication with flash memory devices, then the protocol provides basic read/write functionality, but it cannot discern different operations (program, sector erase, block erase, chip erase) limiting control capability
Solution Approach 1:
The patent embeds an operation mode bit within the existing I2C protocol message structure, nesting the new functionality inside the conventional protocol framework. The mode bit is integrated into the message transmitted between master and slave devices, allowing multiple levels of information (address, read/write bit, operation mode) to be conveyed through a unified communication channel without disrupting the original protocol operation
Solution Approach 2:
The patent adds a new dimension to the I2C protocol by introducing an operation mode bit that extends the message structure. This additional bit dimension enables the protocol to convey operation type information (program, erase, read modes) without altering the fundamental two-wire communication architecture, effectively adding informational depth to the existing protocol plane
2Adaptability or versatility
If additional bits are added to the I2C protocol to indicate operation modes, then precise control of flash memory operations is enabled, but the protocol complexity increases
Solution Approach 1:
The patent segments the I2C message into distinct functional components: address bits, read/write bit, and operation mode bit. This segmentation allows each component to serve a specific purpose while maintaining clear boundaries between them, making the extended protocol easier to parse and implement despite the added complexity
Solution Approach 2:
The extended I2C message structure serves multiple functions simultaneously: it identifies the slave device, determines read/write direction, and specifies the operation mode. This multi-functionality consolidates what would otherwise require separate signaling mechanisms into a single unified message format, reducing overall system complexity despite the added operational capability
Data Source
AI summary
An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.