I2C Bus Glitch Detection Circuit for Start Signal Integrity
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Solution Overview
Problem
I2C bus waveform deformations, caused by glitch signals, lead to malfunctioning of slave devices due to misinterpretation of signal levels, making it difficult to detect errors and ensure correct data transmission.
Innovation Solution
A control circuit with input ends for receiving data and clock signals, a counter to measure low-level periods, a comparator to compare measurement times with threshold values, and an error detector to generate flags for abnormal signal detection, utilizing threshold values defined by I2C bus specifications to prevent misinterpretation of signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the I2C bus uses transistors to realize level shift to convert voltage, then voltage conversion between 3V and 5V is achieved, but glitch signals are generated on the clock signal causing waveform deformation
Solution Approach 1:
The patent applies preliminary action by measuring the low-level period duration of the clock signal before the slave device interprets it as a start signal. The counter counts clock cycles during the low-level period, and this measurement is compared against a threshold value (tLOW) defined in the I2C specification. This preliminary measurement allows the system to detect potential glitch signals before they cause misinterpretation of signal transitions, preventing malfunction proactively.
Solution Approach 2:
The patent implements feedback by continuously monitoring the clock signal's low-level period and comparing it against the specified threshold. The error detector receives the counted value from the counter and generates an error flag when the measured period deviates from the expected range. This feedback mechanism allows the master device to detect waveform deformations caused by glitch signals and take corrective action, such as ignoring malformed start signals.
2Productivity
If the slave device monitors I2C bus signals, then data transmission is enabled, but misinterpretation of glitch signals as start signals causes malfunction
Solution Approach 1:
The patent applies preliminary action by requiring the master device to verify the clock signal's low-level period duration before the slave device interprets signal transitions. The counter measures the number of clock cycles during the low-level period, and this measurement is compared against the tLOW threshold defined in the I2C specification. This preliminary verification ensures that only properly formed start signals are recognized, preventing the slave device from misinterpreting glitch signals.
Solution Approach 2:
The patent implements feedback by having the master device continuously monitor the clock signal characteristics and generate error flags when anomalies are detected. The error detector compares the measured low-level period against the expected threshold and provides feedback to the master device. This feedback loop ensures that the slave device only processes valid signals, maintaining reliable data transmission while enabling continuous monitoring.
3Reliability
If error detection is added to detect waveform deformations, then malfunction prevention is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by utilizing existing I2C bus components (the clock signal itself and standard I2C specification parameters) to perform error detection. The counter uses the clock signal's own low-level period to detect errors, and the threshold value is derived from the I2C specification's tLOW parameter. This approach enables error detection without requiring external monitoring equipment or complex additional circuits, as the system uses its own operational parameters for self-diagnosis.
Solution Approach 2:
The patent implements parameter changes by focusing detection on a specific parameter (the low-level period duration of the clock signal) rather than monitoring all signal characteristics. By measuring only the clock cycle count during the low-level period and comparing it against the tLOW threshold, the system achieves effective error detection with minimal additional complexity. This selective parameter monitoring simplifies the detection mechanism compared to comprehensive waveform analysis.
Data Source
AI summary
A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.