Dual-Address I2C Logic Circuitry for Print Component Validation

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Solution Overview

Problem

Current print systems face challenges in securely and efficiently communicating with replaceable print components, particularly in authenticating and validating the identity and status of these components, which affects the quality and reliability of print operations.

Innovation Solution

The implementation of a dual-address logic circuitry package within print components that uses I2C communications, where a first address is used for primary operations and a second address is activated for specific tasks or validation processes, allowing for secure and efficient communication and authentication protocols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single address is used for logic circuitry in print components, then the device complexity is reduced, but the security and reliability of communication are compromised

Engineering Contradiction:
Improveauthentication securityVSAvoidaddressing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The logic circuitry is divided into multiple functional blocks (first logic circuit, second logic circuit, third logic circuit) that can be independently activated based on the address received. Each block handles specific authentication or communication tasks, allowing secure multi-address operation without requiring the entire circuitry to be complex for each function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The logic circuitry dynamically changes its operational state based on the received address. When a first address is received, the first logic circuit is activated; when a second address is received, the second logic circuit is activated. This dynamic switching enables the same physical circuitry to serve multiple addresses securely without permanent hardware complexity.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If multiple logic circuits are implemented for different addresses, then the authentication capability is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveauthentication capabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Multiple logic circuits (first, second, and third logic circuits) are merged into a single integrated logic circuitry package. The circuits share common infrastructure such as the I2C interface, power supply, and physical substrate, reducing manufacturing complexity while maintaining the ability to perform multiple authentication functions when different addresses are received.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The logic circuitry is designed as a universal package that can handle multiple addresses and authentication protocols through software or control logic configuration rather than dedicated hardware for each function. The same physical circuitry can be programmed or controlled to serve different authentication purposes, simplifying manufacturing while maintaining versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If address switching is implemented for secure communication, then the communication security is improved, but the processing time increases

Engineering Contradiction:
Improvecommunication securityVSAvoidaddress switching time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The logic circuitry is pre-configured with multiple logic circuits and address mapping information during manufacturing. When an address is received, the appropriate logic circuit is already prepared and can be activated immediately without extensive setup or configuration time, minimizing the address switching delay while maintaining security.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3718039B1Logic circuitry
Publication Date: 2021.08.18 HEWLETT PACKARD DEVELOPMENT COMPANY LP
  • EP3718039B1 patent drawingFigure 1~3
  • EP3718039B1 patent drawingFigure 4A~4B
  • EP3718039B1 patent drawingFigure 4C~4D

AI summary

A logic circuit for a replaceable print component is configured to, in response to a series of commands including a first command specifying the new I2C communications address and a first calibration parameter, a second command specifying the new I2C communications address and a second calibration parameter, a third command specifying the new I2C communications address and a class parameter, and/or fourth commands specifying the new I2C communications address and subclass parameters, and at least one read request, generate count values in a count value range defined by a highest and lowest count value.