I2C Noise Removal Latching Circuit for Signal Integrity
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Solution Overview
Problem
In I2C serial data communication, noise superimposed on clock and data signals can cause malfunctions during transmission between master and slave devices.
Innovation Solution
A serial data communication method and device that utilize a noise removal section to latch and remove noise from clock and data signals using a higher frequency signal, specifically a noise removal clock signal, to prevent malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If I2C serial transmission is used for high-speed communication between master and slave devices, then communication speed is improved, but noise susceptibility increases causing malfunctions
Solution Approach 1:
The patent applies preliminary action by latching the clock signal and data signal at predetermined timings before they are fully processed. The latching circuit captures signals at specific moments (when SCL transitions from H to L and SDA is stable), preparing clean, noise-free versions of these signals in advance. This preliminary latching action ensures that even if noise is superimposed later during transmission, the originally latched clean signals can be used for reliable communication.
Solution Approach 2:
The patent implements beforehand cushioning by using latching circuits that capture and hold clean versions of clock and data signals before noise can corrupt them during transmission. The latched signals serve as a cushion or buffer against subsequent noise interference. By establishing clean reference signals in advance through latching, the system creates a protective mechanism that cushions against the harmful effects of noise superposition during high-speed I2C communication.
2Productivity
If noise is superimposed on clock or data signals during I2C communication, then signal integrity deteriorates, but the system continues operating without error detection
Solution Approach 1:
The patent implements feedback by using the latched clock signal to control the timing of data sampling. The latched clean clock signal provides feedback information about the proper sampling moments, ensuring that data is read at the correct timings when it is most reliable. This feedback mechanism allows the system to automatically adjust its sampling timing based on the actual signal conditions, maintaining signal accuracy even in the presence of noise during continuous operation.
Data Source
AI summary
A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.