I2C Physical Layer Interface for Transaction Merging
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Solution Overview
Problem
Existing serial bus protocols like I2C and I3C face inefficiencies due to increased overhead and reduced throughput caused by uncoordinated streams of data, leading to latency and reduced data transfer rates.
Innovation Solution
A physical layer interface that buffers and combines multiple single-byte write transactions into multi-byte transactions, optimizing data transfer by incrementally checking address sequences and using a compressor to append data bytes, thereby reducing overhead and enhancing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single-byte transactions are transmitted individually over the serial bus, then protocol simplicity is maintained, but data transfer throughput is reduced and overhead increases
Solution Approach 1:
The patent combines multiple single-byte transactions into a single multi-byte transaction by buffering incoming transactions in a FIFO buffer and merging them when they share the same slave address and have incrementally increasing register addresses. This merging process reduces the number of individual transactions on the bus, thereby increasing throughput and reducing overhead while maintaining protocol compatibility.
Solution Approach 2:
The patent performs preliminary actions by buffering and pre-processing transactions before they are transmitted over the bus. The physical layer interface accumulates transactions in a FIFO buffer, checks for mergeability conditions (same slave address, incremental register addresses), and prepares merged multi-byte transactions in advance, which are then transmitted efficiently without stalling.
2Loss of time
If multiple single-byte transactions are transmitted sequentially, then address verification is simplified, but transmission latency increases
Solution Approach 1:
The patent implements feedback mechanisms where the physical layer interface continuously monitors incoming transactions, compares register addresses against previously transmitted addresses for the same slave device, and dynamically adjusts transaction merging based on whether addresses are incrementally increasing. This feedback loop ensures accurate address verification while enabling latency reduction through efficient merging when conditions are met.
3Productivity
If transaction buffering is implemented to enable merging, then data transfer efficiency is improved, but buffer management complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the FIFO buffer automatically manages transaction accumulation and the physical layer interface autonomously performs address comparison and merging decisions without requiring complex external control logic. The system serves itself by continuously monitoring transaction streams and making merge decisions based on predefined criteria, reducing the need for complex buffer management overhead.
Data Source
AI summary
Systems, methods, and apparatus are described that enable a physical layer interface of a device coupled to a serial bus to combine two or more single-byte write transactions to obtain a multi-byte write transaction. A method includes buffering a first single-byte transaction addressed to a first register at a first address of a slave device in a first-in-first-out buffer of the physical layer, receiving at the physical layer a second single-byte transaction addressed to a second register at a second address of the slave device coupled to the serial bus, determining in the physical layer whether the second address is incrementally greater than the first address, combining the second single-byte transaction with the first single-byte transaction to obtain a multi-byte transaction, replacing the first single-byte transaction with the multi-byte transaction in the first-in-first-out buffer, and transmitting a sequence of transactions output by the first-in-first-out buffer over the serial bus.