Transient Active Pull-Up I2C for Faster Bus Speed at Lower Power
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Solution Overview
Problem
Existing I2C-bus compatible devices face a trade-off between increasing bus speed and reducing average power consumption, as faster speeds require lower resistance pull-up resistors, which increase power demand.
Innovation Solution
The implementation of a transient active pull-up I2C (TAP-I2C) module with high-side driver transistors on the SDA and SCL lines, which precharges bus capacitance during logic level transitions, allowing for faster data transfer while reducing the need for strong pull-up resistors and thus lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If lower resistance pull-up resistors are used to increase bus speed, then bus speed is improved, but average power consumption increases
Solution Approach 1:
The patent applies preliminary action by precharging the bus capacitance before data transitions occur. The high-side driver transistors are activated in advance to charge the SDA and SCL lines, so that when actual data transitions are needed, the bus is already prepared and can switch faster without requiring low-resistance pull-up resistors during normal operation.
Solution Approach 2:
The patent implements periodic action by using transient active pull-up pulses at specific intervals during bus operations. Instead of continuously activating strong pull-up resistors, the system applies brief periodic charge pulses to the bus lines only when needed for transitions, reducing average power consumption while maintaining high-speed capability when required.
2Speed
If transient active pull-up is used to precharge bus capacitance, then bus speed is improved, but device complexity increases
Solution Approach 1:
The patent merges the transient active pull-up functionality with the existing open-drain I2C bus structure. The high-side driver transistors are integrated into the I2C module alongside the standard open-drain outputs, combining two different bus driving approaches into a unified system that maintains compatibility while adding enhanced performance.
Solution Approach 2:
The patent introduces an intermediary control mechanism that manages when the high-side drivers are activated. Control logic acts as an intermediary between the standard I2C protocol and the transient active pull-up function, determining optimal moments to apply charge pulses without disrupting normal I2C operations or requiring fundamental changes to the bus protocol.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster I2C bus speeds of up to 5-10 MHz while reducing power consumption by using higher resistance pull-up resistors only for maintaining logic levels, rather than charging bus capacitance, thereby accelerating data transfer operations and decreasing overall power usage.
Implementation Method 1
precharge the capacitance of the SDA line and then precharge the capacitance of the SCL line during low to high logic level transitions
Implementation Method 2
the output I2C bus driver resumes its normal open drain configuration which allows the pull-up resistor to simply maintain the voltage (charge) on the SCL and SDA lines
Data Source
AI summary
An I2C-bus compatible device when functioning as a clock master comprises a transient active pull-up I2C (“TAP-I2C”) logic module having high side driver transistors, e.g., P-channel field effect transistors (FETs), coupled between a positive supply voltage and respective serial data (“SDA”) and serial clock (“SCL”) lines on the I2C bus. The high side output driver transistors for the SDA and SCL lines are sequentially pulsed on by the TAP I2C logic module for brief periods to first precharge the capacitance of the SDA line and then precharge the capacitance of the SCL line during low to high logic level transitions thereof. Precharging the capacitances of the I2C bus lines will also accelerate bus transfer operations for all I2C compatible devices since the capacitances of the I2C bus lines will be charged much faster through the low impedance active pull-up driver transistors then through the passive pull-up resistors.