Clock-Synchronized I2C Pull-Up Circuit for Faster Low-Power Data Lines
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Solution Overview
Problem
Existing data communication systems, such as those using the I2C bus, face a trade-off between increasing communication speed and reducing electronic current consumption, with existing pull-up circuit configurations being complex and inefficient in enhancing communication speed without compromising power efficiency.
Innovation Solution
A data communication system that includes a clock signal line, a data signal line, and a pull-up control circuit connected to a second pull-up resistor, which strengthens the pull-up of the data signal line in response to the clock signal, synchronizing the transition time from low to high levels and reducing electronic current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the resistance value of the pull-up resistor is reduced to improve communication speed, then the transition time is shortened, but the pull-up current increases and transistor driving performance decreases
Solution Approach 1:
The patent applies dynamics by making the pull-up resistor value changeable during operation. The switching circuit dynamically switches between a first pull-up resistor (higher resistance) and a second pull-up resistor (lower resistance) based on the communication phase, allowing the system to optimize between power consumption and communication speed at different times rather than using a fixed resistance value.
Solution Approach 2:
The patent implements periodic action by using a clock signal to periodically switch between different pull-up resistor values. The switching circuit responds to clock signal edges to alternately connect the first and second pull-up resistors, creating a rhythmic pattern of high-speed communication phases followed by low-power phases, which resolves the contradiction between speed and power consumption over time.
2Speed
If a pull-up circuit is added to strengthen pull-up current, then the transition time is shortened, but the circuit configuration becomes complicated and cost increases
Solution Approach 1:
The patent applies universality by designing a switching circuit that serves multiple functions: it acts as a selector between different pull-up resistors, responds to clock signal edges, and dynamically adjusts the pull-up strength. This single multi-functional circuit replaces what would otherwise require separate dedicated circuits for each function, simplifying the overall design while achieving the desired performance.
3Speed
If the pull-up current is increased continuously, then the communication speed is improved, but the electronic current consumption increases significantly
Solution Approach 1:
The patent implements periodic action by using a clock signal to periodically switch between different pull-up resistor values. The switching circuit responds to clock signal edges to alternately connect the first and second pull-up resistors, creating a rhythmic pattern of high-speed communication phases followed by low-power phases, which resolves the contradiction between speed and power consumption over time.
Solution Approach 2:
The patent applies dynamics by making the pull-up resistor value changeable during operation. The switching circuit dynamically switches between a first pull-up resistor (higher resistance) and a second pull-up resistor (lower resistance) based on the communication phase, allowing the system to optimize between power consumption and communication speed at different times rather than using a fixed resistance value.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased communication speed without significant increases in electronic current consumption, while maintaining a simple circuit configuration and reducing costs by minimizing external components.
Implementation Method 1
a pull-up resistor connected between the data signal line and a wiring of a power supply potential on a higher potential side
Implementation Method 2
when the transistor is turned on, a low level potential is output to the signal line by the transistor, and when the transistor is turned off, a high level potential is supplied to the signal line via the pull-up resistor
Data Source
AI summary
A data communication system has a first data communication circuit for outputting a clock signal to a clock signal line, receiving data input from a data signal line, and outputting data as open drain output to the data signal line, a second data communication circuit for receiving input of a clock signal from the clock signal line, receiving input of data from the data signal line, and outputting data as open drain output to the data signal line, a first pull-up resistor connected between the data signal line and the wiring of a power supply potential, a second pull-up resistor for selectively pulling up the data signal line, and a pull-up control circuit that is connected to the second pull-up resistor, and strengthens pull-up of the data signal line at least in response to a clock signal.