I2C Read-Write Device Instruction Queue and Processor Task Switching
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Solution Overview
Problem
In the autonomous driving field, the existing I2C interface configuration for image sensors results in low instruction execution efficiency and poor performance due to processors waiting continuously for successful writes to I2C read and write devices, leading to inefficient task processing.
Innovation Solution
An SoC with a processor, I2C read and write device, and I2C controller is designed to stop writing instructions after consecutive unsuccessful attempts and perform other tasks, allowing the I2C read and write device to parse and merge instructions, and the I2C controller to perform control operations based on generated I2C instructions, improving efficiency by handling multiple instructions and data caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor continuously waits for successful write operations to the I2C read and write device, then the reliability of instruction transmission is improved, but the instruction execution efficiency deteriorates
Solution Approach 1:
The patent implements a write counter mechanism that preliminarily counts consecutive unsuccessful write attempts before the processor enters a waiting state. When the counter reaches threshold N, the processor stops continuous write attempts and performs other tasks, while the I2C read and write device continues to process instructions in its instruction queue. This preliminary counting action prevents unnecessary waiting and improves instruction execution efficiency while maintaining reliable instruction transmission through the queued instructions.
2Productivity
If the processor performs multiple tasks concurrently instead of waiting for I2C writes, then the instruction execution efficiency is improved, but the complexity of task coordination increases
Solution Approach 1:
The patent introduces an intermediary mechanism - the write counter and threshold N - that mediates between the processor and the I2C read and write device. This intermediary automatically manages task switching by counting unsuccessful writes and triggering processor suspension when the threshold is reached, eliminating the need for complex software-based task coordination while improving instruction execution efficiency.
3Device complexity
If the I2C read and write device processes instructions sequentially, then the simplicity of the processing mechanism is maintained, but the processing speed deteriorates
Solution Approach 1:
The I2C read and write device maintains an instruction queue that preliminarily stores multiple instructions before processing. This allows the device to continue processing queued instructions even when the processor is suspended due to consecutive write failures, effectively parallelizing the processing pipeline and improving overall processing speed while maintaining the simplicity of sequential instruction handling within the queue.
Data Source
AI summary
A System on a Chip (SoC), a processor and an instruction processing method are provided. The SoC includes a processor, an Inter-Integrated Circuit (I2C) read and write device and an I2C controller, wherein the processor is configured to: write a target instruction to the I2C read and write device; and stop writing the target instruction to the I2C read and write device and performing another task in response to detecting that a number of times that the target instruction has not been successfully written to the I2C read and write device consecutively reaches N, where N>=2; the I2C read and write device is configured to parse the target instruction, and generate and output an I2C instruction corresponding to the target instruction; and the I2C controller is configured to perform a control operation on a connected slave device based on the I2C instruction. Instruction execution efficiency and performance of the processor may be improved.