Multi-Address I2C Selection Circuit for Pin-Constrained Addressing
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Solution Overview
Problem
Existing I2C systems face challenges in selecting unique addresses for multiple I2C chips of the same type, leading to address collisions, and increasing the number of address pins is costly and inefficient.
Innovation Solution
A multi-address I2C selection circuit that uses a single or multiple identification (ID) pins to determine up to 4N selectable I2C addresses by selectively coupling signals and employing XOR gates, flip-flops, and multiplexers to detect and lock the address selection during the initialization phase, avoiding the need for extra pins or programmable IDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of address pins is increased to select more unique addresses, then the address selection capability is improved, but the chip size, package size, and manufacturing cost increase
Solution Approach 1:
The patent implements dynamic address selection by utilizing the I2C bus signal transitions (rising/falling edges) combined with the ID pin state to determine the slave address. This dynamic approach allows 4N address selections using only N pins, as the address is formed by combining pin states with signal edge detections during the initialization phase, rather than requiring static additional pins for each address combination.
Solution Approach 2:
The patent changes the parameter interpretation by using the same physical pin (ID pin) to represent multiple address bits through different signal transition patterns. By detecting rising or falling edges on the SDA line during initialization and combining this with the ID pin voltage level, the system encodes 4N address combinations into a single pin's operational states, effectively changing how address information is represented.
2Adaptability or versatility
If mask programmable or one-time programmable IDs are used to increase address variety, then the address selection capability is improved, but the production cost and marketing logistics increase
Solution Approach 1:
The patent implements self-service address configuration where the device automatically determines its own address during the I2C initialization phase by detecting the combination of ID pin state and SDA signal transitions. This eliminates the need for external programming equipment, mask programming, or one-time programmable memory, as the address is self-configured through the standard I2C bus communication protocol without requiring special manufacturing processes.
Solution Approach 2:
The patent replaces the mechanical/physical programming methods (mask programming, OTP memory) with an electronic/software-based address configuration system. Instead of physically programming unique IDs during manufacturing, the system uses electronic signal detection and logic operations during initialization to determine addresses, substituting a simpler electronic process for more complex manufacturing processes.
3Device complexity
If a fixed internal address setting is used to eliminate address pins, then the device complexity is reduced, but the adaptability to different addresses is lost
Solution Approach 1:
The patent transforms the fixed address concept into a dynamic, configurable address system. Instead of a hard-coded fixed address, the system dynamically determines the slave address by combining the ID pin state with the detection of rising or falling edges on the SDA line during initialization. This dynamic mechanism allows the same hardware to serve multiple address configurations without requiring additional pins or changing the internal address architecture.
Data Source
AI summary
This document discusses, among other things, a multi-address Inter-Integrated Circuit (I2C) selection circuit configured to receive a number (N) of identification (ID) signals from a corresponding number (N) of ID pins of a slave I2C device and at least one of a data signal from a serial data line (SDA) of an I2C bus or a clock signal from a serial clock line (SCL) of the I2C bus, and to determine one of 4 to the power of N (4N) selectable I2C addresses using the number (N) of ID signals and at least one of the data signal or the clock signal. In an example, the multi-address I2C selection circuit can determine 4 selectable I2C addresses using a single ID signal from a single ID pin of the slave I2C device.