I2C Slave Device Clock Power Management via Shadow Registers
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Solution Overview
Problem
In electronic systems using the I2C bus, slave devices operating in a synchronous domain face challenges in reducing power consumption while maintaining data integrity during transitions from a power save mode to a normal power mode, as the oscillator and band gap voltage reference experience variable delays in turning on, potentially leading to missed transactions.
Innovation Solution
A method and apparatus that powers off selective components like the device clock and band gap voltage reference in idle mode, using shadow registers to capture and store data communications during the transition period, ensuring data integrity and reducing power consumption by only activating these components when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the slave device operates in power save mode with oscillator and band gap voltage reference turned off, then power consumption is reduced, but data transactions may be missed due to variable turn-on delay
Solution Approach 1:
The shadow register captures data communication from the asynchronous I2C bus before the oscillator and band gap voltage reference are fully operational. This preliminary capture action stores the data temporarily, ensuring no data is lost during the power-on transition period when the synchronous logic is not yet ready to receive data.
Solution Approach 2:
The shadow register acts as an intermediary buffer between the asynchronous I2C bus and the synchronous slave device logic. It decouples the data capture function from the oscillator-dependent synchronous logic, allowing data to be stored reliably even when the oscillator is transitioning from power-off to power-on state.
2Reliability
If the oscillator and band gap voltage reference are always on to ensure data capture, then data transaction reliability is improved, but power consumption increases
Solution Approach 1:
The slave device is segmented into two functional paths: an asynchronous path using the I2C bus clock for data capture in shadow registers, and a synchronous path using the device clock for data transfer to the register map. This segmentation allows the asynchronous path to operate independently of the oscillator's power state, enabling power savings while maintaining reliability.
Solution Approach 2:
The oscillator and band gap voltage reference are activated periodically only when needed - specifically, when data communication is captured in the shadow register, the device is woken up and the oscillator is enabled to transfer data to the register map. This periodic activation rather than continuous operation reduces power consumption while ensuring functionality when required.
3Loss of information
If shadow registers are used to capture data during transition, then data integrity is maintained, but device complexity increases
Solution Approach 1:
The shadow register creates a copy of the data communication received from the I2C bus during the transition period. This copy mechanism preserves the original data integrity while allowing the main synchronous logic to initialize without pressure to process data immediately. The copy is then transferred to the register map once the oscillator is stable.
Data Source
AI summary
In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode.