I2C Slave Interface Delay Element Configuration for Collision Suppression

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Solution Overview

Problem

Conventional I2C interfaces face issues with collisions between multiple devices on the bus, particularly when slow slave units are operated in different modes, leading to erroneous signal interpretations due to production tolerances and environmental influences, which are not optimally addressed by using only two delay elements.

Innovation Solution

The implementation of three delay elements, specifically asynchronous analog delay elements, allows for optimal suppression of false start/stop signal generation and detection by configuring the delay times to maximize specific time differences and sums, ensuring compliance with I2C protocol specifications and allowing for flexible adaptation to different devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two delay elements are used in conventional I2C interfaces, then some collision problems are suppressed, but optimal suppression of false start/stop signal generation and detection cannot be achieved due to different delay time effects on different problems

Engineering Contradiction:
Improvesignal interpretation accuracyVSAvoidnumber of delay elements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the delay function into three separate delay elements (first delay element for clock line rising edge, second delay element for clock line falling edge, third delay element for data line) instead of using a single or two delay elements. Each delay element is independently configured to address specific collision problems, allowing optimal suppression of false start/stop signal generation and detection while maintaining signal synchronization.

Inventive Principle:
Principle #1Segmentation

2Reliability

If delay times are increased to suppress false start/stop signal detection, then signal interpretation accuracy improves, but transmission speed decreases

Engineering Contradiction:
Improvefalse start/stop signal suppressionVSAvoiddata transmission speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies different delay time characteristics to different parts of the signal transmission: the first delay element has a first delay time for clock rising edges, the second delay element has a second delay time for clock falling edges, and the third delay element has a third delay time for data line transitions. This localized optimization allows each delay element to be tuned independently for its specific function, suppressing false signals while minimizing impact on overall transmission speed.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If I2C interface operates in normal mode with slow slave units, then compatibility is maintained, but collision problems between multiple devices increase

Engineering Contradiction:
Improvecompatibility with slow slave unitsVSAvoidcollision prevention
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements dynamic delay adjustment where the delay elements can be configured with different delay times based on the operating mode and device characteristics. The system adapts the delay parameters to match the speed characteristics of connected slave units, whether operating in standard mode (100 kHz), fast mode (400 kHz), or other modes, thereby preventing collisions while maintaining compatibility with slow slave units.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9025716B2Inter-integrated circuit-slave interface, and method for operating an inter-integrated circuit-slave interface
Publication Date: 2015.05.05 ROBERT BOSCH GMBH
  • US9025716B2 patent drawing
  • US9025716B2 patent drawing
  • US9025716B2 patent drawing

AI summary

An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line being provided for the transmission of a data input signal and a data output signal, the clock line being provided for the transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element. A method for operating an I2C slave interface is also provided.