I2C Slave Device Programmable Output Bank Update Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing I2C communication systems lack efficient methods for programmably updating slave device output banks, particularly in scenarios where simultaneous or sequential updates are required, leading to inefficiencies in data transfer and device configuration.
Innovation Solution
The implementation of a communications system using an I2C serial data bus with programmable registers in slave devices, allowing for sequential or simultaneous updates of output drivers based on configuration settings, utilizing a control bit to determine update events on either the ACKNOWLEDGE or STOP clock pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional I2C communication systems use fixed update cycles for slave device output banks, then device configuration is simple, but data transfer efficiency is poor and cannot meet simultaneous or sequential update requirements
Solution Approach 1:
The patent implements dynamic update cycles for slave device output banks by introducing a control bit that can be programmed to select between different update modes (sequential or simultaneous). This allows the system to adapt its behavior based on application requirements, transforming a static configuration into a dynamic one that can switch between different operational modes to optimize data transfer efficiency for different scenarios.
2Speed
If slave device output banks are updated simultaneously, then update speed is fast, but control flexibility is reduced
Solution Approach 1:
The control bit enables the system to dynamically switch between simultaneous update mode (for high speed requirements) and sequential update mode (for flexible control requirements). This dynamic configurability resolves the contradiction by allowing the system to adapt its update behavior based on the specific application needs, rather than being fixed in one mode.
Solution Approach 2:
The patent changes the update behavior parameter by introducing a programmable control bit that modifies the update cycle timing. By programmably selecting between different update events (ACKNOWLEDGE or STOP clock pulses), the system can adjust its update parameters to match the required control flexibility while maintaining the ability to achieve fast simultaneous updates when needed.
3Adaptability or versatility
If slave device output banks are updated sequentially, then control flexibility is improved, but data transfer time increases
Solution Approach 1:
The programmable control bit allows the system to dynamically select between sequential and simultaneous update modes. When control flexibility is required, the system can operate in sequential mode; when speed is critical, it can switch to simultaneous mode. This dynamic selection capability resolves the time-loss issue by allowing the system to choose the faster simultaneous mode when control flexibility is not the primary requirement.
4Adaptability or versatility
If I2C bus uses standard communication protocol without programmable update control, then protocol simplicity is maintained, but application versatility is limited
Solution Approach 1:
The patent enhances the universality of the I2C slave device by adding a programmable control bit that enables multiple update modes (sequential and simultaneous) within the same device architecture. This single additional feature allows the device to serve multiple application requirements without requiring different hardware designs, thereby improving application versatility while maintaining protocol simplicity.
Solution Approach 2:
The patent introduces a programmable parameter (control bit) that modifies the update behavior of the slave device without changing the fundamental I2C communication protocol. This parameter change approach allows the same protocol to support multiple update modes, enhancing application versatility while avoiding the need to complicate the protocol specification.
Data Source
AI summary
Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers. Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its programmable register.