I2C Start/Stop Detection Circuit Without High-Frequency Sampling
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Solution Overview
Problem
Conventional I2C bus implementations require high-frequency sampling to detect START and STOP bit sequences, leading to increased power consumption and potential glitches due to complex detection circuitry.
Innovation Solution
A serial, half-duplex start/stop event detection circuit that uses the serial clock line as data input and is clocked by the serial data line, ensuring stable detection without dedicated sampling clocks and using safe flip-flop constructs to prevent glitches, with additional buffer flip-flops for self-recovery and asynchronous reset mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-frequency sampling is used to detect START and STOP bit sequences, then detection accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using the existing I2C clock signal (SCL) to periodically sample the data line (SDA) only when necessary - specifically when SCL transitions from low to high state. This replaces continuous high-frequency sampling with event-driven periodic sampling, reducing power consumption while maintaining detection accuracy for START and STOP conditions.
Solution Approach 2:
The detection circuit uses the I2C bus's own clock signal (SCL) to trigger sampling operations, making the system self-service. The clock line automatically provides the timing reference needed for detection without requiring an external dedicated sampling clock, thereby eliminating the power-hungry separate clock generation while ensuring accurate detection at appropriate moments.
2Difficulty of detecting and measuring
If complex detection circuitry is used to detect START and STOP bit sequences, then detection capability is improved, but circuit stability deteriorates due to glitches
Solution Approach 1:
The patent introduces an intermediary element - a flip-flop - that mediates between the raw SDA/SCL signals and the detection logic. The flip-flop captures the SDA state only when SCL is high, acting as a buffer that prevents direct interaction between the data line transitions and the detection circuitry. This intermediary prevents glitches from propagating through the system while maintaining accurate detection of START and STOP conditions.
Solution Approach 2:
The detection circuit is segmented into distinct functional blocks: a sampling stage using the flip-flop triggered by SCL, a detection stage that monitors the sampled SDA value, and a control stage that generates detection signals. This segmentation isolates the glitch-prone sampling operation from the detection logic, improving overall circuit stability while maintaining detection capability.
3Measurement precision
If dedicated sampling clock is used for high-frequency sampling, then sampling accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by making the I2C clock line (SCL) serve dual functions: its primary function of clocking data transfers and its secondary function of triggering sampling operations for START/STOP detection. This eliminates the need for a dedicated sampling clock, reducing device complexity while maintaining sampling accuracy through the reuse of an existing high-frequency signal.
Solution Approach 2:
The patent merges the sampling clock function with the existing I2C clock signal. Instead of having separate clock generators for data transfer and sampling, the design combines these functions into a single clock source (SCL), thereby reducing the number of components and simplifying the overall device architecture while preserving the necessary sampling accuracy.
Data Source
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AI summary
A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop (18) clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output (10) indicative of a stop event. A start detection flip-flop (20), clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output (12) indicative of a start event. A first buffer flip-flop (22), clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop (24), clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output (14). The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.