I2C Start-Stop Detection Circuit Without High-Frequency Sampling
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Solution Overview
Problem
Conventional I2C bus implementations require high-frequency sampling to detect START and STOP bit sequences, leading to increased power consumption and potential glitches due to complex detection circuitry, which can cause erroneous detections and bus lock-ups.
Innovation Solution
A serial, half-duplex start/stop event detection circuit using flip-flops clocked by the serial data input and clock lines, with buffer flip-flops to ensure safe constructs and self-recovery from glitches, eliminating the need for a dedicated sampling clock and preventing flip-flops from resetting their own inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-frequency sampling is used to detect START and STOP bit sequences, then detection accuracy is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic clock signals (SCL and SDA) to sample the bus lines only at relevant transitions rather than continuous high-frequency sampling. The detection circuit responds to specific edge transitions (rising or falling edges) of the clock signal, enabling accurate START/STOP bit detection while significantly reducing power consumption by activating detection only when needed.
Solution Approach 2:
The detection circuit uses the existing I2C bus clock signal itself to drive the sampling process, eliminating the need for a separate high-frequency sampling clock. The SCL and SDA lines serve dual purposes: both as data/clock carriers and as sampling clocks for the detection flip-flops, thereby reducing overall system power consumption.
2Difficulty of detecting and measuring
If complex detection circuitry is used to detect START and STOP bit sequences, then detection capability is improved, but glitches and erroneous detections increase
Solution Approach 1:
The detection circuit is divided into separate, specialized flip-flops for detecting different conditions: one flip-flop for START bit detection, another for STOP bit detection, and additional flip-flops for monitoring SCL and SDA lines. Each segment handles a specific detection task independently, reducing the complexity of any single detection unit and minimizing the risk of glitches while maintaining comprehensive detection capability.
Solution Approach 2:
The patent introduces intermediate flip-flops and signal conditioning stages between the raw bus signals and the final detection logic. These intermediary elements (such as the flip-flops clocked by SCL and SDA) act as buffers and validators, ensuring that only valid, glitch-free transitions trigger detection events, thereby improving reliability without sacrificing detection capability.
3Device complexity
If flip-flops reset their own inputs to avoid dedicated sampling clocks, then circuit complexity is reduced, but erroneous detections occur
Solution Approach 1:
Instead of allowing flip-flops to reset their own inputs (which causes erroneous detections), the patent inverts the approach by using the bus clock signals (SCL and SDA) to externally control and reset the flip-flops. The flip-flops are clocked by the same signals they detect, creating a synchronized system where the clock edges naturally reset the flip-flop states without causing self-induced errors, thus maintaining both simplicity and reliability.
Data Source
AI summary
A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.