I2C Interface State Machines Eliminate Glitches
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Solution Overview
Problem
The existing I2C bus communication protocol faces challenges in efficiently managing multiple features and eliminating glitches and race conditions during data transfers, particularly in the design and generation of control signals for slave/master interfacing.
Innovation Solution
The implementation of two foreground state machines responsive to the rising edge of the clock signal and a background state machine responsive to the falling edge of the clock signal, which conform to write and read states respectively, streamlines the design and eliminates the need for 'glue' logic, thereby addressing issues of glitches and race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional I2C interface design is used with multiple state machines and glue logic, then multiple features can be implemented, but glitches and race conditions occur during data transfers
Solution Approach 1:
The patent divides the I2C interface into separate functional blocks: a state machine generator that produces control signals, a data transfer engine that executes transfers, and a configuration register that sets parameters. This segmentation eliminates the need for complex glue logic between multiple state machines while maintaining multiple feature support through modular design.
Solution Approach 2:
The patent introduces a configuration register as an intermediary between the control logic and data transfer engine. This register holds control signals and parameters that mediate the interaction between different functional blocks, eliminating direct complex interconnections and reducing glitches and race conditions.
2Adaptability or versatility
If complex glue logic is used to manage state machines, then multiple features can be supported, but design complexity increases
Solution Approach 1:
The patent implements a universal data transfer engine that can handle multiple I2C features (read, write, repeated start, stop conditions) through a single unified structure. The engine responds to control signals from the state machine generator to perform different operations, eliminating the need for separate state machines for each feature and reducing overall design complexity.
Solution Approach 2:
The patent uses configuration registers to change parameters that control the data transfer engine's behavior. By modifying register values rather than changing the underlying hardware structure, the system supports multiple features with simple parameter adjustments, significantly reducing design complexity compared to implementing separate state machines for each feature.
Data Source
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AI summary
Consistent with one example embodiment, communications systems, using a serial data transfer bus (125) having a serial data line and a clock line used to implement a communications protocol, incorporate enhanced slave/master interfacing on an I2C bus using state machines. The communications system includes a first and second state- machine (150,160) responsive to the rising edge of the clock signal (134) , and a third state- machine, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal. One of the first state-machine and the second state-machine conform to write states of the communications protocol, and the other of the first state- machine and the second state-machine (170) conform to read states of the communications protocol.