Programmable I2C Interface Thresholds for Multi-Voltage Noise Rejection

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Solution Overview

Problem

Existing I²C interface circuits face challenges in achieving compatibility with multiple pull-up voltage levels while maintaining sufficient hysteresis, leading to noise interference and pin count limitations in low-cost devices.

Innovation Solution

An I²C interface circuit with programmable comparator stages that switch between operating modes based on received pull-up voltage values, allowing compatibility with different voltage levels without the need for additional pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the hysteresis voltage difference (V_IH - V_IL) is increased to accommodate threshold mismatch and provide noise rejection, then noise rejection capability is improved, but compatibility with multiple pull-up voltage levels (1.8V and 3.3V) deteriorates because the threshold values become constrained

Engineering Contradiction:
Improvenoise rejection capabilityVSAvoidcompatibility with multiple pull-up voltage levels
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The comparator thresholds are made dynamic and reconfigurable through programmable logic. The circuit can switch between different threshold configurations (first configuration for 1.8V pull-up, second configuration for 3.3V pull-up) based on detected programming frames, allowing the hysteresis window to adapt to different voltage domains while maintaining adequate noise rejection for each specific configuration

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the electrical parameters (threshold voltages V_IH and V_IL) of the comparator based on the operating conditions. By detecting the pull-up voltage level through programming frames and adjusting the comparator thresholds accordingly, the circuit maintains optimal hysteresis (0.27V difference) for noise rejection while being compatible with multiple pull-up voltage levels

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If an external pull-up voltage pin is added to receive V pu for achieving large hysteresis and multi-voltage compatibility, then adaptability is improved, but device complexity and pin count increase

Engineering Contradiction:
Improvecompatibility with multiple pull-up voltage levelsVSAvoidpin count and PCB trace requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The existing I²C interface pins serve multiple functions: they act as both data/SCL pins for normal I²C communication and as input channels for receiving programming frames that convey pull-up voltage level information. This eliminates the need for dedicated external pull-up voltage pins while maintaining the ability to detect and adapt to different voltage levels

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit performs self-configuration by automatically detecting the pull-up voltage level through the programming frames received on the existing I²C pins and autonomously adjusting its comparator thresholds accordingly. This self-service capability eliminates the need for external pins or manual configuration, reducing both pin count and device complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4583404B1I2c interface circuit, corresponding electronic device and method of operation
Publication Date: 2026.04.22 STMICROELECTRONICS INT NV
  • EP4583404B1 patent drawingFigure 1~2
  • EP4583404B1 patent drawingFigure 3~4
  • EP4583404B1 patent drawing

AI summary

An I2C interface circuit (10; 30; 40) is operatable at a low pull-up voltage and at a high pull-up voltage. A first pin (12a) receives a clock signal (I2Cclk) and a second pin (12b) receives a data signal (I2Cdata). A first comparator stage (24a) compares the received clock signal to a low threshold and a high threshold to produce an internal clock signal (clk_in). A second comparator stage (24b) compares the received data signal to the low threshold and the high threshold to produce an internal data signal (data_in). The first comparator stage and the second comparator stage are programmed by default to operate in a first operating mode, wherein the low threshold is set to a first fractional value of the high pull-up voltage and the high threshold is set to a second fractional value of the low pull-up voltage. The first comparator stage and the second comparator stage are switchable, upon reception via the I2C interface of a programming frame that conveys a current value of the pull-up voltage, to a second operating mode. In the second operating mode, the low threshold is set to the first fractional value of the current pull-up voltage and the high threshold is set to the second fractional value of the current pull-up voltage.