Invalid-to-Modified Cache Protocol for Multi-Core Systems
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Solution Overview
Problem
In multi-processor computing systems, the conventional Request for Ownership (RFO) operations consume significant bandwidth and reduce CPU performance due to the need for frequent invalidation and data propagation across caches and main memory, leading to increased power consumption.
Innovation Solution
The implementation of an Invalid-to-Modified (I2M) operation protocol reduces the number of RFO operations by converting RFO requests, thereby minimizing data transmission and enhancing CPU performance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RFO operations are used to maintain cache coherency, then cache coherency is maintained, but bandwidth usage increases and CPU performance decreases
Solution Approach 1:
The patent changes the operational parameters of cache coherency maintenance by introducing a new I2M protocol that modifies how invalidation requests are handled. Instead of the conventional RFO operation that requires data fetching and propagation, the I2M protocol changes the state parameters directly, allowing processors to modify cache lines without fetching data from main memory, thus reducing bandwidth usage and improving CPU performance while maintaining coherency
Solution Approach 2:
The patent inverts the conventional approach to cache invalidation. Rather than requiring a processor to fetch data and propagate it to other caches (RFO), the system allows direct modification of cache lines in an invalid-to-modified state. This inversion eliminates the need for data fetching and propagation, reducing bandwidth consumption and improving performance while still maintaining cache coherency through the modified state tracking
2Reliability
If conventional RFO operations are used to propagate data across caches, then cache coherency is maintained, but power consumption increases
Solution Approach 1:
The I2M protocol changes the energy consumption parameters by eliminating data fetching and propagation operations. By allowing direct state transitions from invalid to modified without requiring data movement across the memory hierarchy, the protocol significantly reduces the energy required for cache coherency maintenance while preserving coherency through state tracking
Solution Approach 2:
The patent extracts the data fetching and propagation steps from the cache invalidation process. By separating the state management function from the data movement function, the system eliminates unnecessary data transmission operations that consume power, keeping only the essential state tracking operations needed to maintain coherency
3Reliability
If frequent data propagation is performed to maintain cache coherency, then cache coherency is maintained, but bandwidth usage increases
Solution Approach 1:
The I2M protocol changes the bandwidth consumption parameters by modifying the data propagation quantity from full cache line transfers to minimal state update signals. By allowing processors to directly modify cache lines in invalid-to-modified state and tracking these modifications through state parameters rather than data propagation, the protocol dramatically reduces bandwidth usage while maintaining coherency
Data Source
AI summary
An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.