I2S Transmit Control System With FIFO Data Alignment
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Solution Overview
Problem
Current implementations of the I2S interface in microcontrollers require time-intensive data processing for 16-bit and 24-bit audio data, as they are typically stored in packed formats, leading to misalignment and truncation issues when directly written into or read from memory, which consumes processing power and complicates data transfer.
Innovation Solution
An enhanced SPI interface that operates in I2S mode, utilizing a FIFO with a control unit and finite state machine to manage data alignment and transfer, allowing direct 32-bit writes and reads, and enabling efficient handling of 16-bit, 24-bit, and 32-bit audio data by breaking down 24-bit data into manageable parts and reassembling it for transmission, reducing the need for extensive preprocessing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If audio data is stored in packed formats in memory, then memory space is optimized, but data alignment and transfer become complex and time-consuming
Solution Approach 1:
The patent implements a FIFO buffer that is pre-configured with alignment logic for different audio data formats (16-bit, 24-bit, 32-bit). The buffer automatically performs the necessary bit-shifting and alignment operations before data is written to or read from memory, eliminating the need for time-consuming preprocessing operations in the main processor while maintaining efficient memory space utilization through packed storage formats.
2Manufacturing precision
If data preprocessing is performed for 16-bit and 24-bit audio data, then proper alignment is achieved, but processing power is consumed
Solution Approach 1:
The patent introduces a FIFO buffer as an intermediary component between the audio data source and the I2S interface. This buffer contains dedicated alignment logic that automatically handles the complex bit-manipulation operations required for 16-bit and 24-bit audio data. By offloading these preprocessing operations to the FIFO's hardware logic rather than using the main processor, the system achieves precise data alignment while minimizing processing power consumption.
3Adaptability or versatility
If multiple I2S channels are implemented, then audio transmission capability is enhanced, but control complexity increases
Solution Approach 1:
The patent merges the control logic for multiple I2S channels into a unified FIFO buffer structure. The FIFO is designed to handle data for multiple channels simultaneously, with a single control unit that manages data alignment and transfer for all channels. This consolidation approach enables enhanced audio transmission capability across multiple channels while reducing control complexity by eliminating the need for separate control logic for each channel.
Data Source
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AI summary
A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.