I2S Bus Inter-Processor Communication for VoIP Latency Reduction
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Solution Overview
Problem
Dual-processor systems face challenges in reliable inter-processor communication, particularly in minimizing latency and jitter in voice communication applications like VoIP, where disparate processors need to work together effectively.
Innovation Solution
A specially-configured serial bus, such as an I2S bus, is used as a general-purpose data link between processors, enabling continuous serial clock signal transmission and synchronized frame exchange, along with a method for the second processor to act as a proxy for network access and configuration, facilitating reliable communication and network address traversal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional communication interfaces are used between disparate processors, then processor isolation and independent operation are maintained, but communication reliability and synchronization are degraded
Solution Approach 1:
The I2S bus, originally designed for audio communication, is repurposed as a universal data link for inter-processor communication. This allows the same physical interface to handle both audio data and general-purpose data transmission between the application processor and DSP, eliminating the need for separate dedicated communication interfaces while maintaining reliable synchronized communication.
Solution Approach 2:
The patent introduces a proxy mechanism where one processor acts as an intermediary for network access on behalf of the other processor. The application processor can access the DSP's network interface through this proxy relationship, enabling network functionality without requiring direct network interface hardware on every processor.
2Loss of time
If separate communication channels are used for each processor, then processor independence is maintained, but latency and jitter in voice communication increase
Solution Approach 1:
The patent merges the audio data path and control data path into a single I2S bus communication channel. By combining these functions on one synchronized bus, the system reduces the number of separate communication interfaces needed and ensures that all data transmission shares a common timing reference, thereby minimizing latency and jitter while enabling efficient processor cooperation.
3Measurement precision
If a continuous serial clock signal is transmitted, then frame synchronization between processors is improved, but power consumption and signal line requirements increase
Solution Approach 1:
The I2S bus maintains a continuous serial clock signal transmission to ensure uninterrupted frame synchronization between processors. This continuous clocking allows for seamless real-time data transfer with precise timing, which is critical for voice communication applications where even微小的 timing variations can cause audible artifacts. The power consumption increase is acceptable given the critical nature of synchronization in audio processing.
Data Source
AI summary
A means for reliable inter-processor communication in a multi-processor system is described. In accordance with one aspect, a specially-configured serial bus is used as a general-purpose data link between a first processor and a second processor. The serial bus may be an Inter-IC Sound (I2S) bus. In accordance with another aspect, a network interface residing on a second processor is made available to a first processor via a data link established over an I2S bus. This allows the second processor to be used as a proxy and to support remote configuration and network address traversal.