I2S and SPI Stream Multiplexing with Timestamped Clock Sync
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-channel signal processing systems face limitations in synchronizing data streams from I2S or SPI formats across asynchronous interfaces, particularly when using multiple microcontrollers, leading to floating delays and restricted channel counts due to hardware resource constraints.
Innovation Solution
The system transforms the standard sampled clock signal (LRCK) or chip select signal (CS) into a LRCKt signal with embedded time stamp and marker codes, allowing for synchronization of discrete samples across channels without additional processor ports, enabling unlimited channel synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple microcontrollers are used to handle increased channel counts, then channel capacity is improved, but synchronization precision deteriorates due to floating delays between controllers
Solution Approach 1:
A centralized master controller acts as an intermediary to receive time stamp information from all channel groups and perform unified time alignment calculations. This mediator coordinates the timing across multiple microcontrollers, ensuring that channel data from different controllers are synchronized with precision without requiring each controller to independently manage synchronization, thus resolving the floating delay problem while maintaining scalability.
Solution Approach 2:
Time stamp information is embedded into the data stream at the source (ADC or channel group level) before data transmission to the main processor. This preliminary tagging of temporal information allows the master controller to perform post-capture time alignment without introducing additional delay during data acquisition, maintaining synchronization precision even as channel count increases across multiple controllers.
2Reliability
If traditional FIFO or FPGA-based synchronization methods are used, then channel data can be buffered, but hardware resource requirements increase and channel count is limited
Solution Approach 1:
The patent replaces hardware-based FIFO buffers and FPGA logic with a software-based time alignment system running on a general-purpose microcontroller. Instead of using dedicated hardware resources for buffering and synchronization, the system uses software algorithms that process time stamp information to achieve time alignment, dramatically reducing hardware resource requirements while maintaining synchronization reliability and enabling unlimited channel expansion.
Solution Approach 2:
The master microcontroller performs multiple functions: it acts as a universal receiver for time stamp information from any number of channel groups, performs centralized time alignment calculations, and coordinates data output. This multi-functional approach eliminates the need for dedicated synchronization hardware for each channel group, reducing overall system complexity while maintaining reliable synchronization across unlimited channels.
3Measurement precision
If time stamp embedding is implemented in hardware, then synchronization precision is improved, but device complexity and resource usage increase
Solution Approach 1:
Each channel group or ADC unit generates and embeds its own time stamp information based on its local clock signal without requiring external hardware assistance. The channel group autonomously tags its data with temporal information, which is then transmitted to the master controller for unified processing. This self-service approach achieves high time measurement precision while minimizing additional hardware complexity at the channel level.
Data Source
AI summary
This invention relates to multichannel signal processing systems using synchronous protocols I2S (Inter-IC Sound Bus) and SPI (Serial Peripheral Bus) for sequenced data exchange, and providing unified synchronization of processed data. The system and method for synchronously multiplexing data streams in the I2S or SPI formats involves transformation of a standard Left/Right Clock (LRCK) sampled pulse signal of the I2S format or a Chip Select (CS) pulse signal of the SPI format into a LRCLt signal comprising a time stamp code and start and end marker codes of the synchronization clock signal, LRCK or CS, respectively. The presence of the marker codes and the time stamp code enables to restore the pulse signal, LRCK or CS, respectively, in the process of data stream program processing and link each discrete sample to the time stamp. The digital stream multiplexing system includes m channel groups for collection of synchronous data in the I2S or SPI synchronous protocol, a clock generator, a host processor and a means of transforming the LRCK or CS signal into the LRCKt signal. The technical effect consists in removal of limitations on a number of fully synchronized data streams in the I2S or SPI formats and, at the same time, simplification of the synchronization system and method and reduction in requirements to hardware resources.